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    Searched refs:SMULO (Results 1 - 19 of 19) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
ISDOpcodes.h 311 SMULO,
SelectionDAGNodes.h 2748 Opc == ISD::USUBO || Opc == ISD::SMULO || Opc == ISD::UMULO));
  /src/external/apache2/llvm/dist/llvm/lib/Target/M68k/
M68kISelLowering.cpp 98 for (auto OP : {ISD::SMULO, ISD::UMULO}) {
1324 case ISD::SMULO:
2105 CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) {
2132 case ISD::SMULO:
2331 case ISD::SMULO:
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
LegalizeVectorOps.cpp 449 case ISD::SMULO:
843 case ISD::SMULO:
SelectionDAGDumper.cpp 305 case ISD::SMULO: return "smulo";
LegalizeIntegerTypes.cpp 156 case ISD::SMULO:
1365 if (N->getOpcode() == ISD::SMULO) {
2178 case ISD::SMULO: ExpandIntRes_XMULO(N, Lo, Hi); break;
3420 unsigned MulOp = Signed ? ISD::SMULO : ISD::UMULO;
LegalizeVectorTypes.cpp 175 case ISD::SMULO:
1070 case ISD::SMULO:
3070 case ISD::SMULO:
SelectionDAG.cpp 3075 case ISD::SMULO:
3899 case ISD::SMULO:
9991 Opcode == ISD::UMULO || Opcode == ISD::SMULO) &&
TargetLowering.cpp 8100 } else if (Signed && isOperationLegalOrCustom(ISD::SMULO, VT)) {
8102 DAG.getNode(ISD::SMULO, dl, DAG.getVTList(VT, BoolVT), LHS, RHS);
8378 bool isSigned = Node->getOpcode() == ISD::SMULO;
8385 // smulo(x, signed_min) is same as umulo(x, signed_min).
LegalizeDAG.cpp 3467 case ISD::SMULO: {
DAGCombiner.cpp 1640 case ISD::SMULO:
4671 bool IsSigned = (ISD::SMULO == N->getOpcode());
4707 // A 1 bit SMULO overflows if both inputs are 1.
SelectionDAGBuilder.cpp 6720 case Intrinsic::smul_with_overflow: Op = ISD::SMULO; break;
  /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
PPCTargetTransformInfo.cpp 557 case Intrinsic::smul_with_overflow: Opcode = ISD::SMULO; break;
  /src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/
SparcISelLowering.cpp 1684 setOperationAction(ISD::SMULO, MVT::i64, Custom);
2937 // Custom lower UMULO/SMULO for SPARC. This code is similar to ExpandNode()
2943 assert((opcode == ISD::UMULO || opcode == ISD::SMULO) && "Invalid Opcode.");
2945 bool isSigned = (opcode == ISD::SMULO);
3064 case ISD::SMULO: return LowerUMULO_SMULO(Op, DAG, *this);
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
TargetLoweringBase.cpp 778 setOperationAction(ISD::SMULO, VT, Expand);
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
SIISelLowering.cpp 763 setOperationAction(ISD::SMULO, MVT::i64, Custom);
4552 case ISD::SMULO:
5137 bool isSigned = Op.getOpcode() == ISD::SMULO;
5143 // smulo(x, signed_min) is same as umulo(x, signed_min).
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64ISelLowering.cpp 555 setOperationAction(ISD::SMULO, MVT::i32, Custom);
556 setOperationAction(ISD::SMULO, MVT::i64, Custom);
2945 case ISD::SMULO:
2948 bool IsSigned = Op.getOpcode() == ISD::SMULO;
4506 case ISD::SMULO:
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86ISelLowering.cpp 945 setOperationAction(ISD::SMULO, MVT::v16i8, Custom);
1348 setOperationAction(ISD::SMULO, MVT::v32i8, Custom);
1647 setOperationAction(ISD::SMULO, MVT::v64i8, Custom);
1952 setOperationAction(ISD::SMULO, VT, Custom);
23556 case ISD::SMULO:
23820 CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) {
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMISelLowering.cpp 4727 case ISD::SMULO:
5445 bool OptimizeMul = (Opc == ISD::SMULO || Opc == ISD::UMULO) &&
5496 bool OptimizeMul = (Opc == ISD::SMULO || Opc == ISD::UMULO) &&

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