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    Searched refs:SMUL_LOHI (Results 1 - 25 of 33) sorted by relevancy

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  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
ISDOpcodes.h 240 /// SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing
243 SMUL_LOHI,
TargetLowering.h 2427 case ISD::SMUL_LOHI:
  /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
Mips16ISelDAGToDAG.cpp 195 case ISD::SMUL_LOHI:
MipsSEISelLowering.cpp 183 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Custom);
194 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Custom);
230 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
277 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
454 case ISD::SMUL_LOHI: return lowerMulDiv(Op, MipsISD::Mult, true, true, DAG);
  /src/external/apache2/llvm/dist/llvm/lib/Target/AVR/
AVRISelDAGToDAG.cpp 474 bool isSigned = N->getOpcode() == ISD::SMUL_LOHI;
538 case ISD::SMUL_LOHI: return selectMultiplication(N);
AVRISelLowering.cpp 162 // Do not use MUL. The AVR instructions are closer to SMUL_LOHI &co.
167 setOperationAction(ISD::SMUL_LOHI, MVT::i16, Expand);
173 setOperationAction(ISD::SMUL_LOHI, MVT::i8, Expand);
  /src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/
SystemZISelLowering.h 92 SMUL_LOHI,
SystemZISelLowering.cpp 211 setOperationAction(ISD::SMUL_LOHI, VT, Custom);
3516 // SystemZISD::SMUL_LOHI returns the low result in the odd register and
3517 // the high result in the even register. ISD::SMUL_LOHI is defined to
3519 lowerGR128Binary(DAG, DL, VT, SystemZISD::SMUL_LOHI,
3541 // the high result in the even register. ISD::SMUL_LOHI is defined to
5405 case ISD::SMUL_LOHI:
5597 OPCODE(SMUL_LOHI);
6656 // multiplication node. The only option for SystemZ is ISD::SMUL_LOHI, and
  /src/external/apache2/llvm/dist/llvm/lib/Target/XCore/
XCoreISelLowering.cpp 97 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Custom);
210 case ISD::SMUL_LOHI: return LowerSMUL_LOHI(Op, DAG);
541 assert(Op.getValueType() == MVT::i32 && Op.getOpcode() == ISD::SMUL_LOHI &&
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
SelectionDAGDumper.cpp 238 case ISD::SMUL_LOHI: return "smul_lohi";
LegalizeDAG.cpp 3273 Node->getOpcode() == ISD::MULHU ? ISD::UMUL_LOHI : ISD::SMUL_LOHI;
3283 case ISD::SMUL_LOHI: {
3320 // and unsigned forms. If the target supports both SMUL_LOHI and
3323 bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, VT);
3329 OpToUse = ISD::SMUL_LOHI;
3333 OpToUse = ISD::SMUL_LOHI;
4526 case ISD::SMUL_LOHI: {
LegalizeVectorOps.cpp 443 case ISD::SMUL_LOHI:
TargetLowering.cpp 5204 if (isOperationLegalOrCustom(ISD::SMUL_LOHI, VT, IsAfterLegalization)) {
5206 DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(VT, VT), X, Y);
6260 Opcode == ISD::SMUL_LOHI);
6267 isOperationLegalOrCustom(ISD::SMUL_LOHI, HiLoVT);
6285 Lo = DAG.getNode(Signed ? ISD::SMUL_LOHI : ISD::UMUL_LOHI, dl, VTs, L, R);
6407 if (!MakeMUL_LOHI(LH, RH, Lo, Hi, Opcode == ISD::SMUL_LOHI))
6419 if (Opcode == ISD::SMUL_LOHI) {
8134 unsigned LoHiOp = Signed ? ISD::SMUL_LOHI : ISD::UMUL_LOHI;
8407 { ISD::MULHS, ISD::SMUL_LOHI, ISD::SIGN_EXTEND }};
  /src/external/apache2/llvm/dist/llvm/lib/Target/BPF/
BPFISelLowering.cpp 110 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
  /src/external/apache2/llvm/dist/llvm/lib/Target/MSP430/
MSP430ISelLowering.cpp 124 setOperationAction(ISD::SMUL_LOHI, MVT::i8, Promote);
129 setOperationAction(ISD::SMUL_LOHI, MVT::i16, Expand);
  /src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/
LanaiISelLowering.cpp 117 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
  /src/external/apache2/llvm/dist/llvm/lib/Target/M68k/
M68kISelLowering.cpp 86 ISD::MULHS, ISD::MULHU, ISD::UMUL_LOHI, ISD::SMUL_LOHI}) {
92 for (auto OP : {ISD::UMUL_LOHI, ISD::SMUL_LOHI}) {
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86ISelDAGToDAG.cpp 2240 case ISD::SMUL_LOHI:
5036 case ISD::SMUL_LOHI:
5043 bool IsSigned = Opcode == ISD::SMUL_LOHI;
  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
HexagonISelLowering.cpp 1587 ISD::SMUL_LOHI, ISD::UMUL_LOHI}) {
1632 ISD::UADDO, ISD::SSUBO, ISD::USUBO, ISD::SMUL_LOHI, ISD::UMUL_LOHI,
  /src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/
SparcISelLowering.cpp 1663 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
1679 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMISelLowering.cpp 773 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
1121 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
4728 // We generate a SMUL_LOHI and then check if all the bits of the high word
4731 Value = DAG.getNode(ISD::SMUL_LOHI, dl,
12082 V->getOpcode() == ISD::SMUL_LOHI)
12171 // If we find this pattern, we can replace the U/SMUL_LOHI, ADDC, and ADDE by
12218 AddcSubcOp0->getOpcode() != ISD::SMUL_LOHI &&
12220 AddcSubcOp1->getOpcode() != ISD::SMUL_LOHI)
12243 unsigned FinalOpc = (Opc == ISD::SMUL_LOHI) ? ARMISD::SMLAL : ARMISD::UMLAL;
12259 // Ensure that LoMul and LowAddSub are taken from correct ISD::SMUL_LOHI nod
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
AMDGPUISelLowering.cpp 370 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
440 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
  /src/external/apache2/llvm/dist/llvm/lib/Target/VE/
VEISelLowering.cpp 170 // VE has no MULHU/S or U/SMUL_LOHI operations.
171 // TODO: Use MPD instruction to implement SMUL_LOHI for i32 type.
175 setOperationAction(ISD::SMUL_LOHI, IntVT, Expand);
  /src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/
WebAssemblyISelLowering.cpp 128 {ISD::BSWAP, ISD::SMUL_LOHI, ISD::UMUL_LOHI, ISD::MULHS, ISD::MULHU,
  /src/external/apache2/llvm/dist/llvm/lib/Target/NVPTX/
NVPTXISelLowering.cpp 498 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);

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