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  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/
dce_dmcu.h 48 SR(SMU_INTERRUPT_CONTROL), \
65 SR(SMU_INTERRUPT_CONTROL), \
107 DMCU_SF(SMU_INTERRUPT_CONTROL, DC_SMU_INT_ENABLE, mask_sh)
125 DMCU_SF(SMU_INTERRUPT_CONTROL, DC_SMU_INT_ENABLE, mask_sh)
182 uint32_t SMU_INTERRUPT_CONTROL;
amdgpu_dce_dmcu.c 653 REG_UPDATE(SMU_INTERRUPT_CONTROL, DC_SMU_INT_ENABLE, 1);

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