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Searched refs:SMU_SCLK_DPM_STATE_0_CNTL_1 (Results 1 - 2 of 2) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/radeon/
trinityd.h	`49 #define SMU_SCLK_DPM_STATE_0_CNTL_1 0x1f004`
radeon_trinity_dpm.c	`623 value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix); 626 WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix, value); 635 value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix); 638 WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix, value); 689 value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix); 692 WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix, value); 701 value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix); 704 WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix, value);`

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