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Searched refs:SMU_SCLK_DPM_STATE_0_CNTL_3 (Results 1 - 2 of 2) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/radeon/
trinityd.h	`63 #define SMU_SCLK_DPM_STATE_0_CNTL_3 0x1f00c`
radeon_trinity_dpm.c	`665 value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_3 + ix); 668 WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_3 + ix, value); 677 value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_3 + ix); 680 WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_3 + ix, value);`

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