HomeSort by: relevance | last modified time | path
    Searched refs:SPLL_CNTL_MODE__SPLL_SW_DIR_CONTROL_MASK (Results 1 - 7 of 7) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/smu/
smu_6_0_sh_mask.h 300 #define SPLL_CNTL_MODE__SPLL_SW_DIR_CONTROL_MASK 0x00000001L
smu_7_0_0_sh_mask.h 209 #define SPLL_CNTL_MODE__SPLL_SW_DIR_CONTROL_MASK 0x1
smu_7_1_1_sh_mask.h 199 #define SPLL_CNTL_MODE__SPLL_SW_DIR_CONTROL_MASK 0x1
smu_7_0_1_sh_mask.h 201 #define SPLL_CNTL_MODE__SPLL_SW_DIR_CONTROL_MASK 0x1
smu_7_1_0_sh_mask.h 199 #define SPLL_CNTL_MODE__SPLL_SW_DIR_CONTROL_MASK 0x1
smu_7_1_2_sh_mask.h 201 #define SPLL_CNTL_MODE__SPLL_SW_DIR_CONTROL_MASK 0x1
smu_7_1_3_sh_mask.h 227 #define SPLL_CNTL_MODE__SPLL_SW_DIR_CONTROL_MASK 0x1

Completed in 81 milliseconds