| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/ |
| dcn20_hubbub.h | 36 SR(DCHUBBUB_CRC_CTRL), \
37 SR(DCN_VM_FB_LOCATION_BASE),\
38 SR(DCN_VM_FB_LOCATION_TOP),\
39 SR(DCN_VM_FB_OFFSET),\
40 SR(DCN_VM_AGP_BOT),\
41 SR(DCN_VM_AGP_TOP),\
42 SR(DCN_VM_AGP_BASE)
49 SR(DCHUBBUB_CRC_CTRL), \
50 SR(DCN_VM_FB_LOCATION_BASE),\
51 SR(DCN_VM_FB_LOCATION_TOP),
[all...] |
| dcn20_dccg.h | 34 SR(DPPCLK_DTO_CTRL),\
39 SR(REFCLK_CNTL)
|
| dcn20_optc.h | 45 SR(DWB_SOURCE_SELECT),\
|
| dcn20_hubp.h | 68 SR(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB),\
69 SR(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB)
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/ |
| dce_hwseq.h | 33 SR(LVTMA_PWRSEQ_CNTL), \
34 SR(LVTMA_PWRSEQ_STATE)
51 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL)
88 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \
89 SR(DCFEV_CLOCK_CONTROL), \
98 SR(BLNDV_CONTROL),\
136 SR(DCHUB_FB_LOCATION),\
137 SR(DCHUB_AGP_BASE),\
138 SR(DCHUB_AGP_BOT),\
139 SR(DCHUB_AGP_TOP),
[all...] |
| dce_dmcu.h | 35 SR(DMCU_CTRL), \
36 SR(DMCU_STATUS), \
37 SR(DMCU_RAM_ACCESS_CTRL), \
38 SR(DMCU_IRAM_WR_CTRL), \
39 SR(DMCU_IRAM_WR_DATA), \
40 SR(MASTER_COMM_DATA_REG1), \
41 SR(MASTER_COMM_DATA_REG2), \
42 SR(MASTER_COMM_DATA_REG3), \
43 SR(MASTER_COMM_CMD_REG), \
44 SR(MASTER_COMM_CNTL_REG),
[all...] |
| dce_abm.h | 35 SR(BL_PWM_PERIOD_CNTL), \
36 SR(BL_PWM_CNTL), \
37 SR(BL_PWM_CNTL2), \
38 SR(BL_PWM_GRP1_REG_LOCK), \
39 SR(LVTMA_PWRSEQ_REF_DIV), \
40 SR(MASTER_COMM_CNTL_REG), \
41 SR(MASTER_COMM_CMD_REG), \
42 SR(MASTER_COMM_DATA_REG1)
46 SR(DC_ABM1_HG_SAMPLE_RATE), \
47 SR(DC_ABM1_LS_SAMPLE_RATE),
[all...] |
| dce_audio.h | 35 SR(AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS),\
36 SR(AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES),\
37 SR(AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES),\
38 SR(DCCG_AUDIO_DTO_SOURCE),\
39 SR(DCCG_AUDIO_DTO0_MODULE),\
40 SR(DCCG_AUDIO_DTO0_PHASE),\
41 SR(DCCG_AUDIO_DTO1_MODULE),\
42 SR(DCCG_AUDIO_DTO1_PHASE)
|
| dce_link_encoder.h | 49 SR(DMCU_RAM_ACCESS_CTRL), \
50 SR(DMCU_IRAM_RD_CTRL), \
51 SR(DMCU_IRAM_RD_DATA), \
52 SR(DMCU_INTERRUPT_TO_UC_EN_MASK), \
78 SR(DCI_MEM_PWR_STATUS)
88 SR(DCI_MEM_PWR_STATUS)
95 SR(DCI_MEM_PWR_STATUS)
101 SR(DCI_MEM_PWR_STATUS)
|
| dce_i2c_hw.h | 90 SR(DC_I2C_ARBITRATION),\
91 SR(DC_I2C_CONTROL),\
92 SR(DC_I2C_SW_STATUS),\
93 SR(DC_I2C_TRANSACTION0),\
94 SR(DC_I2C_TRANSACTION1),\
95 SR(DC_I2C_TRANSACTION2),\
96 SR(DC_I2C_TRANSACTION3),\
97 SR(DC_I2C_DATA),\
98 SR(MICROSECOND_TIME_BASE_DIV)
|
| dce_mem_input.h | 81 SR(DCHUB_FB_LOCATION),\
82 SR(DCHUB_AGP_BASE),\
83 SR(DCHUB_AGP_BOT),\
84 SR(DCHUB_AGP_TOP)
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn21/ |
| dcn21_hubbub.h | 33 SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_A),\
34 SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_B),\
35 SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_C),\
36 SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_D),\
37 SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A),\
38 SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B),\
39 SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C),\
40 SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D),\
41 SR(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A),\
42 SR(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B),
[all...] |
| dcn21_link_encoder.h | 85 SR(RDPCSTX0_RDPCSTX_SCRATCH)
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/ |
| dcn10_hubbub.h | 38 SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A),\
39 SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A),\
40 SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B),\
41 SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B),\
42 SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C),\
43 SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C),\
44 SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D),\
45 SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D),\
46 SR(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL),\
47 SR(DCHUBBUB_ARB_DRAM_STATE_CNTL),
[all...] |
| /src/sys/arch/mips/mips/ |
| cache_tx39_subr.S | 55 mfc0 t0, MIPS_COP_0_STATUS # Save SR.
84 mtc0 t0, MIPS_COP_0_STATUS # Restore SR.
102 mfc0 t0, MIPS_COP_0_STATUS # Save SR.
131 mtc0 t0, MIPS_COP_0_STATUS # Restore SR.
|
| cache_r3k_subr.S | 150 mfc0 t0, MIPS_COP_0_STATUS # Save SR.
174 mtc0 t0, MIPS_COP_0_STATUS # Restore SR.
192 mfc0 t0, MIPS_COP_0_STATUS # Save SR.
218 mtc0 t0, MIPS_COP_0_STATUS # Restore SR.
|
| spl.S | 67 * a0 = SR bits to be cleared for this IPL
134 INT_L a1, (v1) # load SR bits for this IPL
137 xor a1, MIPS_INT_MASK # invert SR bits
160 INT_L a1, (v1) # load SR bits for this IPL
353 INT_L ta2, (ta3) # get SR bits for ipl in ta2
|
| /src/sys/arch/luna68k/stand/boot/ |
| locore.S | 202 movw #PSL_HIGHIPL,%sr | no interrupts
253 movw #PSL_LOWIPL,%sr | enable interrupts
262 movw #PSL_HIGHIPL,%sr | no interrupts
278 clrw %sp@- | pad SR to longword
354 movw %sp@,%sp@(12) | yes, push down SR
362 movw %sp@,%sp@(24) | yes, push down SR
368 movw %sp@,%sp@(84) | type 11, push down SR
418 clrw %sp@- | pad SR to longword
559 clrw %sp@- | pad SR to longword
578 movw %sp@,%sp@(12) | yes, push down SR
[all...] |
| /src/sys/arch/newsmips/stand/boot/ |
| locore.S | 68 mfc0 v0, MIPS_COP_0_STATUS # save SR
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/hw/ |
| clk_mgr_internal.h | 94 SR(DENTIST_DISPCLK_CNTL)
102 SR(DENTIST_DISPCLK_CNTL), \
|
| /src/sys/arch/m68k/060sp/dist/ |
| changes | 87 SR = SR at time of exception
109 SR = SR at time of exception
|
| iskeletn.s | 102 # * SR * * SR *
140 # * SR * * SR *
|
| /src/sys/arch/pmax/pmax/ |
| locore_machdep.S | 148 mfc0 v0, MIPS_COP_0_STATUS # save original SR in v0
160 mtc0 v0, MIPS_COP_0_STATUS # restore SR on exit
|
| /src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/ |
| imx6ul-prti6g.dts | 219 /* SR */
232 /* SR */
|
| /src/sys/arch/atari/atari/ |
| locore.s | 381 movw %sp@(20),%sp@- | push previous SR value
387 movw %sr,%d2 | Block interrupts for now
388 oriw #0x0700,%sr
397 movew %d2,%sr | Re-enable interrupts
418 movw %sr,%d1 | goto splhigh
419 oriw #0x0700,%sr
431 movw %d1,%sr | splx
439 movw %sr,%d1 | goto splhigh
440 oriw #0x0700,%sr
445 movw %d1,%sr | spl
[all...] |
