| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/ |
| dce_clock_source.h | 62 SRII(PHASE, DP_DTO, 0),\
63 SRII(PHASE, DP_DTO, 1),\
64 SRII(PHASE, DP_DTO, 2),\
65 SRII(PHASE, DP_DTO, 3),\
66 SRII(PHASE, DP_DTO, 4),\
67 SRII(PHASE, DP_DTO, 5),\
68 SRII(MODULO, DP_DTO, 0),\
69 SRII(MODULO, DP_DTO, 1),\
70 SRII(MODULO, DP_DTO, 2),\
71 SRII(MODULO, DP_DTO, 3),
[all...] |
| dce_hwseq.h | 45 SRII(DCFE_CLOCK_CONTROL, DCFE, 0), \
46 SRII(DCFE_CLOCK_CONTROL, DCFE, 1), \
47 SRII(DCFE_CLOCK_CONTROL, DCFE, 2), \
48 SRII(DCFE_CLOCK_CONTROL, DCFE, 3), \
49 SRII(DCFE_CLOCK_CONTROL, DCFE, 4), \
50 SRII(DCFE_CLOCK_CONTROL, DCFE, 5), \
54 SRII(BLND_V_UPDATE_LOCK, BLND, 0), \
55 SRII(BLND_V_UPDATE_LOCK, BLND, 1), \
56 SRII(BLND_V_UPDATE_LOCK, BLND, 2), \
57 SRII(BLND_V_UPDATE_LOCK, BLND, 3),
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/ |
| dcn20_mpc.h | 37 SRII(MPCC_TOP_GAIN, MPCC, inst),\
38 SRII(MPCC_BOT_GAIN_INSIDE, MPCC, inst),\
39 SRII(MPCC_BOT_GAIN_OUTSIDE, MPCC, inst),\
40 SRII(MPCC_OGAM_RAMA_START_CNTL_B, MPCC_OGAM, inst),\
41 SRII(MPCC_OGAM_RAMA_START_CNTL_G, MPCC_OGAM, inst),\
42 SRII(MPCC_OGAM_RAMA_START_CNTL_R, MPCC_OGAM, inst),\
43 SRII(MPCC_OGAM_RAMA_SLOPE_CNTL_B, MPCC_OGAM, inst),\
44 SRII(MPCC_OGAM_RAMA_SLOPE_CNTL_G, MPCC_OGAM, inst),\
45 SRII(MPCC_OGAM_RAMA_SLOPE_CNTL_R, MPCC_OGAM, inst),\
46 SRII(MPCC_OGAM_RAMA_END_CNTL1_B, MPCC_OGAM, inst),
[all...] |
| dcn20_dwb.h | 51 #define SRII(reg_name, block, id)\
|
| dcn20_mmhubbub.h | 53 #define SRII(reg_name, block, id)\
|
| amdgpu_dcn20_resource.c | 395 #define SRII(reg_name, block, id)\
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/ |
| dcn10_mpc.h | 36 SRII(MPCC_TOP_SEL, MPCC, inst),\
37 SRII(MPCC_BOT_SEL, MPCC, inst),\
38 SRII(MPCC_CONTROL, MPCC, inst),\
39 SRII(MPCC_STATUS, MPCC, inst),\
40 SRII(MPCC_OPP_ID, MPCC, inst),\
41 SRII(MPCC_BG_G_Y, MPCC, inst),\
42 SRII(MPCC_BG_R_CR, MPCC, inst),\
43 SRII(MPCC_BG_B_CB, MPCC, inst),\
44 SRII(MPCC_BG_B_CB, MPCC, inst),\
45 SRII(MPCC_SM_CONTROL, MPCC, inst
[all...] |
| dcn10_dwb.h | 47 #define SRII(reg_name, block, id)\
|
| amdgpu_dcn10_resource.c | 185 #define SRII(reg_name, block, id)\
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce100/ |
| amdgpu_dce100_resource.c | 486 #define SRII(reg_name, block, id)\
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce120/ |
| amdgpu_dce120_resource.c | 754 #define SRII(reg_name, block, id)\
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce110/ |
| amdgpu_dce110_resource.c | 536 #define SRII(reg_name, block, id)\
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce112/ |
| amdgpu_dce112_resource.c | 513 #define SRII(reg_name, block, id)\
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce80/ |
| amdgpu_dce80_resource.c | 609 #define SRII(reg_name, block, id)\
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn21/ |
| amdgpu_dcn21_resource.c | 306 #define SRII(reg_name, block, id)\
|
