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    Searched refs:SRL_PARTS (Results 1 - 24 of 24) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
ISDOpcodes.h 702 /// SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded
707 SRL_PARTS,
  /src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/
LanaiISelLowering.cpp 122 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
196 case ISD::SRL_PARTS:
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
SelectionDAGDumper.cpp 313 case ISD::SRL_PARTS: return "srl_parts";
LegalizeDAG.cpp 1221 case ISD::SRL_PARTS:
LegalizeIntegerTypes.cpp 3748 PartsOpc = ISD::SRL_PARTS;
SelectionDAG.cpp 7985 case ISD::SRL_PARTS:
  /src/external/apache2/llvm/dist/llvm/lib/Target/BPF/
BPFISelLowering.cpp 114 setOperationAction(ISD::SRL_PARTS, VT, Expand);
  /src/external/apache2/llvm/dist/llvm/lib/Target/MSP430/
MSP430ISelLowering.cpp 113 setOperationAction(ISD::SRL_PARTS, MVT::i8, Expand);
114 setOperationAction(ISD::SRL_PARTS, MVT::i16, Expand);
  /src/external/apache2/llvm/dist/llvm/lib/Target/NVPTX/
NVPTXISelLowering.cpp 397 setOperationAction(ISD::SRL_PARTS, MVT::i32 , Custom);
400 setOperationAction(ISD::SRL_PARTS, MVT::i64 , Custom);
1939 /// LowerShiftRightParts - Lower SRL_PARTS, SRA_PARTS, which
1947 assert(Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS);
2180 case ISD::SRL_PARTS:
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
R600ISelLowering.cpp 194 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
456 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
SIISelLowering.cpp 236 setOperationAction(ISD::SRL_PARTS, MVT::i64, Expand);
  /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
MipsISelLowering.cpp 377 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
383 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
1228 case ISD::SRL_PARTS: return lowerShiftRightParts(Op, DAG, false);
  /src/external/apache2/llvm/dist/llvm/lib/Target/AVR/
AVRISelLowering.cpp 90 setOperationAction(ISD::SRL_PARTS, MVT::i16, Expand);
  /src/external/apache2/llvm/dist/llvm/lib/Target/XCore/
XCoreISelLowering.cpp 103 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
  /src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/
SparcISelLowering.cpp 1654 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
1688 setOperationAction(ISD::SRL_PARTS, MVT::i64, Expand);
  /src/external/apache2/llvm/dist/llvm/lib/Target/VE/
VEISelLowering.cpp 165 // VE has no SHL_PARTS/SRA_PARTS/SRL_PARTS operations.
168 setOperationAction(ISD::SRL_PARTS, IntVT, Expand);
  /src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/
WebAssemblyISelLowering.cpp 130 ISD::SRL_PARTS, ISD::ADDC, ISD::ADDE, ISD::SUBC, ISD::SUBE}) {
  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
HexagonISelLowering.cpp 1586 ISD::SHL_PARTS, ISD::SRA_PARTS, ISD::SRL_PARTS,
  /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
PPCISelLowering.cpp 690 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
695 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
10826 case ISD::SRL_PARTS: return LowerSRL_PARTS(Op, DAG);
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMISelLowering.cpp 1129 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
1146 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
6027 assert(Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS);
9882 case ISD::SRL_PARTS:
  /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/
RISCVISelLowering.cpp 237 setOperationAction(ISD::SRL_PARTS, XLenVT, Custom);
1940 case ISD::SRL_PARTS:
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64ISelLowering.cpp 402 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
4588 case ISD::SRL_PARTS:
7609 /// LowerShiftParts - Lower SHL_PARTS/SRA_PARTS/SRL_PARTS, which returns two
  /src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/
SystemZISelLowering.cpp 289 setOperationAction(ISD::SRL_PARTS, MVT::i64, Expand);
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86ISelLowering.cpp 493 setOperationAction(ISD::SRL_PARTS, VT, Custom);
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