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    Searched refs:SRW (Results 1 - 14 of 14) sorted by relevancy

  /src/external/gpl3/binutils/dist/opcodes/
rl78-decode.opc 127 #define SRW(r) OP (1, RL78_Operand_Register, RW(r), 0)
280 ID(add); W(); DR(AX); SRW(rw); Fzac;
546 ID(cmp); W(); DR(AX); SRW(ra); Fzac;
862 ID(mov); W(); DR(AX); SRW(ra);
1000 ID(mov); W(); DPUSH(); SRW(rg);
1198 ID(sub); W(); DR(AX); SRW(rw); Fzac;
1245 ID(xch); W(); DR(AX); SRW(ra);
rl78-decode.c 129 #define SRW(r) OP (1, RL78_Operand_Register, RW(r), 0)
235 ID(add); W(); DR(AX); SRW(rw); Fzac;
481 ID(mov); W(); DR(AX); SRW(ra);
641 ID(sub); W(); DR(AX); SRW(rw); Fzac;
1250 ID(xch); W(); DR(AX); SRW(ra);
1439 ID(cmp); W(); DR(AX); SRW(ra); Fzac;
5057 ID(mov); W(); DPUSH(); SRW(rg);
  /src/external/gpl3/binutils.old/dist/opcodes/
rl78-decode.opc 127 #define SRW(r) OP (1, RL78_Operand_Register, RW(r), 0)
280 ID(add); W(); DR(AX); SRW(rw); Fzac;
546 ID(cmp); W(); DR(AX); SRW(ra); Fzac;
862 ID(mov); W(); DR(AX); SRW(ra);
1000 ID(mov); W(); DPUSH(); SRW(rg);
1198 ID(sub); W(); DR(AX); SRW(rw); Fzac;
1245 ID(xch); W(); DR(AX); SRW(ra);
rl78-decode.c 129 #define SRW(r) OP (1, RL78_Operand_Register, RW(r), 0)
235 ID(add); W(); DR(AX); SRW(rw); Fzac;
481 ID(mov); W(); DR(AX); SRW(ra);
641 ID(sub); W(); DR(AX); SRW(rw); Fzac;
1250 ID(xch); W(); DR(AX); SRW(ra);
1439 ID(cmp); W(); DR(AX); SRW(ra); Fzac;
5057 ID(mov); W(); DPUSH(); SRW(rg);
  /src/external/gpl3/gdb.old/dist/opcodes/
rl78-decode.opc 127 #define SRW(r) OP (1, RL78_Operand_Register, RW(r), 0)
280 ID(add); W(); DR(AX); SRW(rw); Fzac;
546 ID(cmp); W(); DR(AX); SRW(ra); Fzac;
862 ID(mov); W(); DR(AX); SRW(ra);
1000 ID(mov); W(); DPUSH(); SRW(rg);
1198 ID(sub); W(); DR(AX); SRW(rw); Fzac;
1245 ID(xch); W(); DR(AX); SRW(ra);
rl78-decode.c 129 #define SRW(r) OP (1, RL78_Operand_Register, RW(r), 0)
235 ID(add); W(); DR(AX); SRW(rw); Fzac;
481 ID(mov); W(); DR(AX); SRW(ra);
641 ID(sub); W(); DR(AX); SRW(rw); Fzac;
1250 ID(xch); W(); DR(AX); SRW(ra);
1439 ID(cmp); W(); DR(AX); SRW(ra); Fzac;
5057 ID(mov); W(); DPUSH(); SRW(rg);
  /src/external/gpl3/gdb/dist/opcodes/
rl78-decode.opc 127 #define SRW(r) OP (1, RL78_Operand_Register, RW(r), 0)
280 ID(add); W(); DR(AX); SRW(rw); Fzac;
546 ID(cmp); W(); DR(AX); SRW(ra); Fzac;
862 ID(mov); W(); DR(AX); SRW(ra);
1000 ID(mov); W(); DPUSH(); SRW(rg);
1198 ID(sub); W(); DR(AX); SRW(rw); Fzac;
1245 ID(xch); W(); DR(AX); SRW(ra);
rl78-decode.c 129 #define SRW(r) OP (1, RL78_Operand_Register, RW(r), 0)
235 ID(add); W(); DR(AX); SRW(rw); Fzac;
481 ID(mov); W(); DR(AX); SRW(ra);
641 ID(sub); W(); DR(AX); SRW(rw); Fzac;
1250 ID(xch); W(); DR(AX); SRW(ra);
1439 ID(cmp); W(); DR(AX); SRW(ra); Fzac;
5057 ID(mov); W(); DPUSH(); SRW(rg);
  /src/sys/external/bsd/sljit/dist/sljit_src/
sljitNativePPC_32.c 218 return push_inst(compiler, SRW | RC(flags) | S(src1) | A(dst) | B(src2));
sljitNativePPC_64.c 354 return push_inst(compiler, ((flags & ALT_FORM2) ? SRW : SRD) | RC(flags) | S(src1) | A(dst) | B(src2));
sljitNativePPC_common.c 212 #define SRW (HI(31) | LO(536))
  /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
PPCInstrInfo.cpp 3923 case PPC::SRW:
3961 case PPC::SRW: III.ImmOpcode = PPC::RLWINM; break;
4954 Opc == PPC::SRW || Opc == PPC::SRW_rec ||
4961 bool RightShift = Opc == PPC::SRW || Opc == PPC::SRW_rec || Opc == PPC::SRD ||
5136 Opcode == PPC::SLW_rec || Opcode == PPC::SRW || Opcode == PPC::SRW_rec ||
PPCISelDAGToDAG.cpp 6649 // SLW and SRW always clear the higher-order bits.
6651 Op32.getMachineOpcode() == PPC::SRW) {
6864 case PPC::SRW: NewOpcode = PPC::SRW8; break;
PPCISelLowering.cpp 11256 // srw SrwDest, tmpDest, shift
11324 BuildMI(BB, dl, TII->get(PPC::SRW), ValueReg)
11366 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW), SrwDestReg)
12270 // srw dest, tmpDest, shift
12372 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW), dest)

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