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Searched refs:SR_SIE (Results 1 - 7 of 7) sorted by relevancy

/src/sys/arch/riscv/include/
intr.h	`144 #define ENABLE_INTERRUPTS() csr_sstatus_set(SR_SIE) 146 #define DISABLE_INTERRUPTS() csr_sstatus_clear(SR_SIE)`
sysreg.h	`211 #define SR_SIE __BIT(1) // Supervisor mode interrupt enable`
/src/sys/arch/riscv/riscv/
cpu_switch.S	`60 csrrci t0, sstatus, SR_SIE // # disable interrupts 177 csrrci t0, sstatus, SR_SIE // disable interrupts 195 csrrci t0, sstatus, SR_SIE // disable interrupts 385 csrsi sstatus, SR_SIE // reenable interrupts 395 csrci sstatus, SR_SIE // disable interrupts 444 csrsi sstatus, SR_SIE // reenable interrupts`
trap.c	`586 KASSERT(__SHIFTOUT(tf->tf_sr, SR_SIE) == 0); 589 csr_sstatus_set(SR_SIE); 633 KASSERT(__SHIFTOUT(tf->tf_sr, SR_SIE) == 0);`
spl.S	`97 csrsi sstatus, SR_SIE // enable interrupts`
riscv_machdep.c	`186 KASSERT(__SHIFTOUT(tf->tf_sr, SR_SIE) == 0); 209 KASSERT(__SHIFTOUT(tf->tf_sr, SR_SIE) == 0); 404 if ((csr_sstatus_read() & SR_SIE) == 0) {`
locore.S	`495 csrsi sstatus, SR_SIE // enable interrupts`

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