| /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| VirtRegMap.h | 153 /// records virtReg is a split live interval from SReg.
154 void setIsSplitFromReg(Register virtReg, Register SReg) {
155 Virt2SplitMap[virtReg.id()] = SReg;
156 if (hasShape(SReg)) {
157 Virt2ShapeMap[virtReg.id()] = getShape(SReg);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| A15SDOptimizer.cpp | 100 unsigned getDPRLaneFromSPR(unsigned SReg);
115 unsigned getPrefSPRLane(unsigned SReg);
144 unsigned A15SDOptimizer::getDPRLaneFromSPR(unsigned SReg) {
145 unsigned DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_1,
153 unsigned A15SDOptimizer::getPrefSPRLane(unsigned SReg) {
154 if (!Register::isVirtualRegister(SReg))
155 return getDPRLaneFromSPR(SReg);
157 MachineInstr *MI = MRI->getVRegDef(SReg);
159 MachineOperand *MO = MI->findRegisterDefOperand(SReg);
165 SReg = MI->getOperand(1).getReg()
[all...] |
| ARMBaseInstrInfo.cpp | 4959 unsigned SReg, unsigned &Lane) {
4960 unsigned DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_0, &ARM::DPRRegClass);
4967 DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_1, &ARM::DPRRegClass);
|
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| LivePhysRegs.cpp | 263 for (MCSuperRegIterator SReg(Reg, &TRI); SReg.isValid(); ++SReg) {
264 if (LiveRegs.contains(*SReg) && !MRI.isReserved(*SReg)) {
|
| RegisterScavenging.cpp | 546 Register SReg = findSurvivorReg(I, Candidates, 25, UseMI);
549 if (!isRegUsed(SReg)) {
550 LLVM_DEBUG(dbgs() << "Scavenged register: " << printReg(SReg, TRI) << "\n");
551 return SReg;
557 ScavengedInfo &Scavenged = spill(SReg, *RC, SPAdj, I, UseMI);
561 << printReg(SReg, TRI) << "\n");
563 return SReg;
654 Register SReg = RS.scavengeRegisterBackwards(RC, DefMI.getIterator(),
656 MRI.replaceRegWith(VReg, SReg);
658 return SReg;
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| SIPreEmitPeephole.cpp | 69 // sreg = -1 or 0
70 // vcc = S_AND_B64 exec, sreg or S_ANDN2_B64 exec, sreg
119 Register SReg;
121 SReg = Op2.getReg();
125 if (M->definesRegister(SReg, TRI))
127 if (M->modifiesRegister(SReg, TRI))
129 ReadsSreg |= M->readsRegister(SReg, TRI);
135 // First if sreg is only used in the AND instruction fold the immediate
168 if (SReg == ExecReg)
[all...] |
| SIShrinkInstructions.cpp | 761 Register SReg = Src2->getReg();
762 if (SReg.isVirtual()) {
763 MRI.setRegAllocationHint(SReg, 0, VCCReg);
766 if (SReg != VCCReg)
|
| SIInstrInfo.cpp | 1057 Register SReg = MRI.createVirtualRegister(BoolXExecRC);
1058 BuildMI(MBB, I, DL, get(AMDGPU::COPY), SReg)
1065 .addReg(SReg);
1070 Register SReg = MRI.createVirtualRegister(BoolXExecRC);
1072 : AMDGPU::S_CSELECT_B64), SReg)
1080 .addReg(SReg);
1084 Register SReg = MRI.createVirtualRegister(BoolXExecRC);
1086 : AMDGPU::S_CSELECT_B64), SReg)
1094 .addReg(SReg);
1100 Register SReg = MRI.createVirtualRegister(BoolXExecRC)
[all...] |
| /src/external/apache2/llvm/dist/clang/include/clang/StaticAnalyzer/Core/PathSensitive/ |
| MemRegion.h | 441 SubRegion(const MemRegion *sReg, Kind k) : MemRegion(k), superRegion(sReg) {
443 assert(sReg);
502 TypedRegion(const MemRegion *sReg, Kind k) : SubRegion(sReg, k) {
526 TypedValueRegion(const MemRegion* sReg, Kind k) : TypedRegion(sReg, k) {
557 CodeTextRegion(const MemSpaceRegion *sreg, Kind k) : TypedRegion(sreg, k) {
576 FunctionCodeRegion(const NamedDecl *fd, const CodeSpaceRegion* sreg)
[all...] |
| /src/external/apache2/llvm/dist/clang/lib/StaticAnalyzer/Core/ |
| MemRegion.cpp | 163 ObjCIvarRegion::ObjCIvarRegion(const ObjCIvarDecl *ivd, const SubRegion *sReg)
164 : DeclRegion(sReg, ObjCIvarRegionKind), IVD(ivd) {}
307 unsigned Idx, const MemRegion *SReg) {
311 ID.AddPointer(SReg);
319 const MemRegion *sreg) {
322 ID.AddPointer(sreg);
369 const MemRegion *sReg) {
374 ID.AddPointer(sReg);
383 const MemRegion *sReg) {
385 ID.AddPointer(sReg);
[all...] |
| /src/external/gpl3/gdb.old/dist/opcodes/ |
| i386-opc.h | 834 SReg, /* Segment register */
|
| i386-gen.c | 513 CLASS (SReg),
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| PPCRegisterInfo.cpp | 1325 SReg = MF.getRegInfo().createVirtualRegister(RC);
1329 BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::LI8 : PPC::LI), SReg)
1334 BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::ORI8 : PPC::ORI), SReg)
1360 MI.getOperand(OperandBase + 1).ChangeToRegister(SReg, false, false, true);
|
| PPCISelLowering.cpp | 11316 Register SReg = RegInfo.createVirtualRegister(GPRC);
11317 BuildMI(BB, dl, TII->get(PPC::AND), SReg)
11320 unsigned ValueReg = SReg;
11325 .addReg(SReg)
|
| /src/external/gpl3/binutils/dist/opcodes/ |
| i386-opc.h | 880 SReg, /* Segment register */
|
| i386-gen.c | 562 CLASS (SReg),
|
| /src/external/gpl3/binutils.old/dist/opcodes/ |
| i386-opc.h | 867 SReg, /* Segment register */
|
| i386-gen.c | 542 CLASS (SReg),
|
| /src/external/gpl3/gdb/dist/opcodes/ |
| i386-opc.h | 867 SReg, /* Segment register */
|
| i386-gen.c | 542 CLASS (SReg),
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/AsmParser/ |
| MipsAsmParser.cpp | 4861 unsigned SReg = Inst.getOperand(1).getReg();
4869 if (DReg == SReg) {
4877 TOut.emitRRR(Mips::ROTRV, DReg, SReg, TmpReg, Inst.getLoc(), STI);
4882 TOut.emitRRR(Mips::ROTRV, DReg, SReg, TReg, Inst.getLoc(), STI);
4908 TOut.emitRRR(FirstShift, ATReg, SReg, ATReg, Inst.getLoc(), STI);
4909 TOut.emitRRR(SecondShift, DReg, SReg, TReg, Inst.getLoc(), STI);
4924 unsigned SReg = Inst.getOperand(1).getReg();
4936 TOut.emitRRI(Mips::ROTR, DReg, SReg, ShiftValue, Inst.getLoc(), STI);
4941 TOut.emitRRI(Mips::ROTR, DReg, SReg, ImmValue, Inst.getLoc(), STI);
4950 TOut.emitRRI(Mips::SRL, DReg, SReg, 0, Inst.getLoc(), STI)
[all...] |
| /src/external/gpl3/binutils/dist/gas/config/ |
| tc-i386-intel.c | 337 if ((i386_regtab[reg_num].reg_type.bitfield.class == SReg
1169 if (i386_regtab[expP->X_add_number].reg_type.bitfield.class != SReg)
|
| tc-i386.c | 3689 case SReg:
3822 || x->types[j].bitfield.class == SReg
3929 { { .bitfield = { .class = SReg } }, "SReg" },
11151 else if (i.types[0].bitfield.class == SReg && !dot_insn ())
15471 if (*op_string == ':' && r->reg_type.bitfield.class == SReg)
16859 || (r->reg_type.bitfield.class == SReg && r->reg_num > 3)
16980 if (r->reg_type.bitfield.class == SReg && r->reg_num == RegFlat
|
| /src/external/gpl3/binutils.old/dist/gas/config/ |
| tc-i386-intel.c | 337 if ((i386_regtab[reg_num].reg_type.bitfield.class == SReg
1169 if (i386_regtab[expP->X_add_number].reg_type.bitfield.class != SReg)
|
| tc-i386.c | 3635 case SReg:
3768 || x->types[j].bitfield.class == SReg
3875 { { .bitfield = { .class = SReg } }, "SReg" },
10984 else if (i.types[0].bitfield.class == SReg && !dot_insn ())
15320 if (*op_string == ':' && r->reg_type.bitfield.class == SReg)
16688 || (r->reg_type.bitfield.class == SReg && r->reg_num > 3)
16809 if (r->reg_type.bitfield.class == SReg && r->reg_num == RegFlat
|
