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  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
HexagonFrameLowering.cpp 1615 BitVector SRegs(Hexagon::NUM_TARGET_REGS);
1617 // Generate a set of unique, callee-saved registers (SRegs), where each
1619 // i.e. for each R in SRegs, no proper super-register of R is also in SRegs.
1622 // sub-registers to SRegs.
1628 SRegs[*SR] = true;
1631 LLVM_DEBUG(dbgs() << "SRegs.1: "; dump_registers(SRegs, *TRI);
1635 // sub- and super-registers from SRegs.
1640 SRegs[*SR] = false
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
SIInstrInfo.cpp 4945 SmallVector<unsigned, 8> SRegs;
4951 SRegs.push_back(SGPR);
4958 MIB.addReg(SRegs[i]);

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