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    Searched refs:SRsrc (Results 1 - 3 of 3) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
AMDGPUISelDAGToDAG.cpp 189 bool SelectMUBUF(SDValue Addr, SDValue &SRsrc, SDValue &VAddr,
192 bool SelectMUBUFAddr64(SDValue Addr, SDValue &SRsrc, SDValue &VAddr,
198 SDValue Addr, SDValue &SRsrc, SDValue &Soffset,
201 bool SelectMUBUFOffset(SDValue Addr, SDValue &SRsrc, SDValue &Soffset,
1473 bool AMDGPUDAGToDAGISel::SelectMUBUFAddr64(SDValue Addr, SDValue &SRsrc,
1493 SRsrc = SDValue(Lowering.wrapAddr64Rsrc(*CurDAG, DL, Ptr), 0);
1592 SDValue &SRsrc,
1603 SRsrc = CurDAG->getRegister(Info->getScratchRSrcReg(), MVT::v4i32);
1617 bool AMDGPUDAGToDAGISel::SelectMUBUFOffset(SDValue Addr, SDValue &SRsrc,
1637 SRsrc = SDValue(Lowering.buildRSRC(*CurDAG, DL, Ptr, 0, Rsrc), 0)
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SILoadStoreOptimizer.cpp 87 bool SRsrc = false;
94 // GFX10 image_sample instructions can have 12 vaddrs + srsrc + ssamp.
433 Result.SRsrc = true;
443 int SRsrcIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::srsrc);
448 Result.SRsrc = true;
459 Result.SRsrc = true;
548 if (Regs.SRsrc)
550 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::srsrc);
1348 MIB.add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::srsrc))
1412 MIB.add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::srsrc))
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SIInstrInfo.cpp 202 !nodesHaveSameOperandValue(Load0, Load1, AMDGPU::OpName::srsrc))
319 const MachineOperand *RSrc = getNamedOperand(LdSt, AMDGPU::OpName::srsrc);
346 int SRsrcIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::srsrc);
4202 int SRsrcIdx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::srsrc);
5202 Register SRsrc = MRI.createVirtualRegister(SRsrcRC);
5205 auto Merge = BuildMI(LoopBB, I, DL, TII.get(AMDGPU::REG_SEQUENCE), SRsrc);
5213 Rsrc.setReg(SRsrc);
5505 MachineOperand *SRsrc = getNamedOperand(MI, AMDGPU::OpName::srsrc);
5506 if (SRsrc && !RI.isSGPRClass(MRI.getRegClass(SRsrc->getReg()))
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