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    Searched refs:SSUBSAT (Results 1 - 18 of 18) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
ISDOpcodes.h 329 SSUBSAT,
TargetLowering.h 2466 case ISD::SSUBSAT:
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86TargetTransformInfo.cpp 2408 { ISD::SSUBSAT, MVT::v32i16, 1 },
2409 { ISD::SSUBSAT, MVT::v64i8, 1 },
2476 { ISD::SSUBSAT, MVT::v32i16, 2 }, // FIXME: include split
2477 { ISD::SSUBSAT, MVT::v64i8, 2 }, // FIXME: include split
2537 { ISD::SSUBSAT, MVT::v16i16, 1 },
2538 { ISD::SSUBSAT, MVT::v32i8, 1 },
2592 { ISD::SSUBSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert
2593 { ISD::SSUBSAT, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert
2700 { ISD::SSUBSAT, MVT::v8i16, 1 },
2701 { ISD::SSUBSAT, MVT::v16i8, 1 }
    [all...]
X86ISelLowering.cpp 962 setOperationAction(ISD::SSUBSAT, MVT::v16i8, Legal);
966 setOperationAction(ISD::SSUBSAT, MVT::v8i16, Legal);
1360 setOperationAction(ISD::SSUBSAT, MVT::v32i8, HasInt256 ? Legal : Custom);
1364 setOperationAction(ISD::SSUBSAT, MVT::v16i16, HasInt256 ? Legal : Custom);
1687 setOperationAction(ISD::SSUBSAT, VT, HasBWI ? Legal : Custom);
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
LegalizeVectorOps.cpp 454 case ISD::SSUBSAT:
847 case ISD::SSUBSAT:
SelectionDAGDumper.cpp 317 case ISD::SSUBSAT: return "ssubsat";
SelectionDAG.cpp 5070 case ISD::SSUBSAT: return C1.ssub_sat(C2);
5569 case ISD::SSUBSAT:
5580 if (Opcode == ISD::SSUBSAT || Opcode == ISD::USUBSAT)
5900 case ISD::SSUBSAT:
5925 case ISD::SSUBSAT:
LegalizeIntegerTypes.cpp 169 case ISD::SSUBSAT:
809 case ISD::SSUBSAT:
2182 case ISD::SSUBSAT:
LegalizeVectorTypes.cpp 130 case ISD::SSUBSAT:
1040 case ISD::SSUBSAT:
3029 case ISD::SSUBSAT:
LegalizeDAG.cpp 1136 case ISD::SSUBSAT:
3373 case ISD::SSUBSAT:
TargetLowering.cpp 7984 case ISD::SSUBSAT:
8345 // If SADDSAT/SSUBSAT is legal, compare results to detect overflow.
8346 unsigned OpcSat = IsAdd ? ISD::SADDSAT : ISD::SSUBSAT;
SelectionDAGBuilder.cpp 6432 setValue(&I, DAG.getNode(ISD::SSUBSAT, sdl, Op1.getValueType(), Op1, Op2));
DAGCombiner.cpp 1613 case ISD::SSUBSAT:
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
TargetLoweringBase.cpp 758 setOperationAction(ISD::SSUBSAT, VT, Expand);
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
SIISelLowering.cpp 453 setOperationAction(ISD::SSUBSAT, MVT::i16, Legal);
455 setOperationAction(ISD::SSUBSAT, MVT::i32, Legal);
679 setOperationAction(ISD::SSUBSAT, MVT::v2i16, Legal);
711 setOperationAction(ISD::SSUBSAT, MVT::v4i16, Custom);
4550 case ISD::SSUBSAT:
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMISelLowering.cpp 222 for (auto Opcode : {ISD::SADDSAT, ISD::UADDSAT, ISD::SSUBSAT, ISD::USUBSAT})
282 setOperationAction(ISD::SSUBSAT, VT, Legal);
1107 setOperationAction(ISD::SSUBSAT, MVT::i8, Custom);
1109 setOperationAction(ISD::SSUBSAT, MVT::i16, Custom);
1113 setOperationAction(ISD::SSUBSAT, MVT::i32, Legal);
9917 case ISD::SSUBSAT:
10017 case ISD::SSUBSAT:
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64ISelLowering.cpp 320 setOperationAction(ISD::SSUBSAT, VT, Legal);
1041 setOperationAction(ISD::SSUBSAT, VT, Legal);
14043 return convertMergedOpToPredOp(N, ISD::SSUBSAT, DAG, true);
14052 return DAG.getNode(ISD::SSUBSAT, SDLoc(N), N->getValueType(0),
  /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
PPCISelLowering.cpp 717 setOperationAction(ISD::SSUBSAT, VT, Legal);

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