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    Searched refs:STEP_0_SPLL_FB_DIV_MASK (Results 1 - 2 of 2) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/radeon/
radeon_r600_dpm.c	501 STEP_0_SPLL_FB_DIV(divider), ~STEP_0_SPLL_FB_DIV_MASK);
r600d.h	1368 # define STEP_0_SPLL_FB_DIV_MASK (0xff << 8)

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