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  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
AMDGPUAsmPrinter.cpp 193 const GCNSubtarget &STM = MF->getSubtarget<GCNSubtarget>();
201 const auto &FunctionTargetID = STM.getTargetID();
224 if ((STM.isMesaKernel(F) || isHsaAbiVersion2(getGlobalSTI())) &&
232 if (STM.isAmdHsaOS())
259 const GCNSubtarget &STM = MF->getSubtarget<GCNSubtarget>();
264 STM, KernelName, getAmdhsaKernelDescriptor(*MF, CurrentProgramInfo),
267 IsaInfo::getNumExtraSGPRs(&STM,
283 const GCNSubtarget &STM = MF->getSubtarget<GCNSubtarget>();
284 if (MFI->isEntryFunction() && STM.isAmdHsaOrMesa(MF->getFunction())) {
426 const GCNSubtarget &STM = MF.getSubtarget<GCNSubtarget>()
    [all...]
R600AsmPrinter.cpp 47 const R600Subtarget &STM = MF.getSubtarget<R600Subtarget>();
48 const R600RegisterInfo *RI = STM.getRegisterInfo();
71 if (STM.getGeneration() >= AMDGPUSubtarget::EVERGREEN) {
SILoadStoreOptimizer.cpp 162 const GCNSubtarget &STM);
181 const GCNSubtarget *STM = nullptr;
489 const GCNSubtarget &STM) {
509 EltSize = AMDGPU::convertSMRDOffsetUnits(STM, 4);
853 bool SILoadStoreOptimizer::widthsFit(const GCNSubtarget &STM,
859 return (Width <= 4) && (STM.hasDwordx3LoadStores() || (Width != 3));
902 (!widthsFit(*STM, CI, Paired) || !offsetsCanBeCombined(CI, *STM, Paired)))
1015 offsetsCanBeCombined(CI, *STM, Paired, true);
1034 if (STM->ldsRequiresM0Init()
    [all...]
AMDGPUHSAMetadataStreamer.cpp 193 const GCNSubtarget &STM = MF.getSubtarget<GCNSubtarget>();
202 HSACodeProps.mKernargSegmentSize = STM.getKernArgSegmentSize(F,
208 HSACodeProps.mWavefrontSize = STM.getWavefrontSize();
213 HSACodeProps.mIsXNACKEnabled = STM.isXNACKEnabled();
852 const GCNSubtarget &STM = MF.getSubtarget<GCNSubtarget>();
860 STM.getKernArgSegmentSize(F, MaxKernArgAlign));
868 Kern.getDocument()->getNode(STM.getWavefrontSize());
SIMemoryLegalizer.cpp 1048 const GCNSubtarget &STM = MBB.getParent()->getSubtarget<GCNSubtarget>();
1050 const unsigned InvalidateL1 = STM.isAmdPalOS() || STM.isMesa3DOS()
  /src/external/apache2/llvm/dist/llvm/lib/IR/
DataLayout.cpp 675 StructLayoutMap *STM = static_cast<StructLayoutMap*>(LayoutMap);
676 StructLayout *&SL = (*STM)[Ty];
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMBaseInstrInfo.cpp 1179 // Fallback to STM instruction, which has existed since the dawn of
1607 MachineInstrBuilder LDM, STM;
1620 STM = BuildMI(*BB, MI, dl, TII->get(isThumb2 ? ARM::t2STMIA_UPD
1625 STM = BuildMI(*BB, MI, dl, TII->get(isThumb2 ? ARM::t2STMIA : ARM::STMIA));
1632 STM.add(STBase).add(predOps(ARMCC::AL));
1647 STM.addReg(Reg, RegState::Kill);
3651 // Return the number of 32-bit words loaded by LDM or stored by STM. If this

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