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    Searched refs:SUBCARRY (Results 1 - 15 of 15) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
ISDOpcodes.h 259 /// FIXME: These nodes are deprecated in favor of ADDCARRY and SUBCARRY.
261 /// toward the use of ADDCARRY/SUBCARRY and will eventually be removed.
284 SUBCARRY,
698 /// (setcccarry lhshi rhshi (subcarry lhslo rhslo) cc).
  /src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/
SystemZISelLowering.h 100 SADDO, SSUBO, UADDO, USUBO, ADDCARRY, SUBCARRY,
SystemZISelLowering.cpp 187 setOperationAction(ISD::SUBCARRY, VT, Custom);
3714 while (Carry.getOpcode() == ISD::SUBCARRY)
3719 // Lower ADDCARRY/SUBCARRY nodes.
3748 case ISD::SUBCARRY:
3752 BaseOp = SystemZISD::SUBCARRY;
5419 case ISD::SUBCARRY:
5606 OPCODE(SUBCARRY);
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
AMDGPUISelLowering.cpp 1875 SDValue Sub1_Lo = DAG.getNode(ISD::SUBCARRY, DL, HalfCarryVT, LHS_Lo,
1877 SDValue Sub1_Hi = DAG.getNode(ISD::SUBCARRY, DL, HalfCarryVT, LHS_Hi,
1895 SDValue Sub2_Lo = DAG.getNode(ISD::SUBCARRY, DL, HalfCarryVT, Sub1_Lo,
1897 SDValue Sub2_Mi = DAG.getNode(ISD::SUBCARRY, DL, HalfCarryVT, Sub1_Mi,
1899 SDValue Sub2_Hi = DAG.getNode(ISD::SUBCARRY, DL, HalfCarryVT, Sub2_Mi,
1915 SDValue Sub3_Lo = DAG.getNode(ISD::SUBCARRY, DL, HalfCarryVT, Sub2_Lo,
1917 SDValue Sub3_Mi = DAG.getNode(ISD::SUBCARRY, DL, HalfCarryVT, Sub2_Mi,
1919 SDValue Sub3_Hi = DAG.getNode(ISD::SUBCARRY, DL, HalfCarryVT, Sub3_Mi,
SIISelLowering.cpp 232 setOperationAction(ISD::SUBCARRY, MVT::i32, Legal);
240 setOperationAction(ISD::SUBCARRY, MVT::i64, Legal);
800 setTargetDAGCombine(ISD::SUBCARRY);
4016 // only from uniform add/subcarry node. All the VGPR operands
10393 // add x, sext (setcc) => subcarry x, 0, setcc
10412 Opc = (Opc == ISD::SIGN_EXTEND) ? ISD::SUBCARRY : ISD::ADDCARRY;
10438 // sub x, zext (setcc) => subcarry x, 0, setcc
10453 Opc = (Opc == ISD::SIGN_EXTEND) ? ISD::ADDCARRY : ISD::SUBCARRY;
10458 if (LHS.getOpcode() == ISD::SUBCARRY) {
10459 // sub (subcarry x, 0, cc), y => subcarry x, y, c
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AMDGPUISelDAGToDAG.cpp 738 case ISD::SUBCARRY:
1010 // FIXME: Should only handle addcarry/subcarry
1111 (!IsAdd && (UI->getOpcode() != ISD::SUBCARRY))) {
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
SelectionDAGDumper.cpp 309 case ISD::SUBCARRY: return "subcarry";
LegalizeIntegerTypes.cpp 162 case ISD::SUBCARRY: Res = PromoteIntRes_ADDSUBCARRY(N, ResNo); break;
1309 // Handle promotion for the ADDE/SUBE/ADDCARRY/SUBCARRY nodes. Notice that
1311 // the ADDCARRY/SUBCARRY nodes in that the third operand is carry Boolean.
1324 // A SUBCARRY can generate borrow only if LHS < RHS and this property will be
1532 case ISD::SUBCARRY: Res = PromoteIntOp_ADDSUBCARRY(N, OpNo); break;
2164 case ISD::SUBCARRY: ExpandIntRes_ADDSUBCARRY(N, Lo, Hi); break;
2564 N->getOpcode() == ISD::ADD ? ISD::ADDCARRY : ISD::SUBCARRY,
2575 Hi = DAG.getNode(ISD::SUBCARRY, dl, VTList, HiOps);
2741 CarryOp = ISD::SUBCARRY;
2813 : ISD::SUBCARRY;
    [all...]
DAGCombiner.cpp 1625 case ISD::SUBCARRY: return visitSUBCARRY(N);
2598 if (V.getOpcode() != ISD::ADDCARRY && V.getOpcode() != ISD::SUBCARRY &&
3044 // And generate ADDCARRY (or SUBCARRY) with two result values:
3048 // Our goal is to identify A, B, and CarryIn and produce ADDCARRY/SUBCARRY with
3078 unsigned NewOp = Opcode == ISD::UADDO ? ISD::ADDCARRY : ISD::SUBCARRY;
3116 // fold (addcarry (xor a, -1), b, c) -> (subcarry b, a, !c) and flip carry.
3120 SDValue Sub = DAG.getNode(ISD::SUBCARRY, DL, N->getVTList(), N1,
3699 // fold (subcarry x, y, false) -> (usubo x, y)
LegalizeDAG.cpp 3408 case ISD::SUBCARRY: {
TargetLowering.cpp 8309 // If ADD/SUBCARRY is legal, use that instead.
8310 unsigned OpcCarry = IsAdd ? ISD::ADDCARRY : ISD::SUBCARRY;
  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
HexagonISelLowering.cpp 1557 setOperationAction(ISD::SUBCARRY, VT, Expand);
1560 setOperationAction(ISD::SUBCARRY, MVT::i64, Custom);
3150 case ISD::SUBCARRY: return LowerAddSubCarry(Op, DAG);
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
TargetLoweringBase.cpp 783 setOperationAction(ISD::SUBCARRY, VT, Expand);
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMISelLowering.cpp 1104 setOperationAction(ISD::SUBCARRY, MVT::i32, Custom);
6616 // ARMISD::SUBE expects a carry not a borrow like ISD::SUBCARRY so we
9263 // ARMISD::SUBE expects a carry not a borrow like ISD::SUBCARRY so we
9277 // by ISD::SUBCARRY, so compute 1 - C.
9909 case ISD::SUBCARRY: return LowerADDSUBCARRY(Op, DAG);
16817 // where t = (SUBCARRY 0, (SUB x, y), 0)
16819 // The SUBCARRY computes 0 - (x - y) and this will give a borrow when
16827 // ISD::SUBCARRY returns a borrow but we want the carry here
16867 // t2 = (SUBCARRY (SUB x, y), t1:0, t1:1)
16874 // t2 = (SUBCARRY x, t1:0, t1:1
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86ISelLowering.cpp 1957 setOperationAction(ISD::SUBCARRY, VT, Custom);
    [all...]

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