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    Searched refs:SUa (Results 1 - 5 of 5) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
AMDGPUExportClustering.cpp 64 SUnit *SUa = Exports[Idx];
76 DAG->addEdge(SUb, SDep(SUa, SDep::Barrier));
78 DAG->addEdge(SUb, SDep(SUa, SDep::Cluster));
  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
ScheduleDAGInstrs.h 204 /// Adds a chain edge between SUa and SUb, but only if both
206 void addChainDependency(SUnit *SUa, SUnit *SUb,
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
ScheduleDAGInstrs.cpp 548 void ScheduleDAGInstrs::addChainDependency (SUnit *SUa, SUnit *SUb,
550 if (SUa->getInstr()->mayAlias(AAForDep, *SUb->getInstr(), UseTBAA)) {
551 SDep Dep(SUa, SDep::MayAliasMem);
MachineScheduler.cpp 1631 SUnit *SUa = MemOpa.SU;
1633 if (SUa->NodeNum > SUb->NodeNum)
1634 std::swap(SUa, SUb);
1637 if (!DAG->addEdge(SUb, SDep(SUa, SDep::Cluster)))
1640 LLVM_DEBUG(dbgs() << "Cluster ld/st SU(" << SUa->NodeNum << ") - SU("
1645 // Copy successor edges from SUa to SUb. Interleaving computation
1646 // dependent on SUa can prevent load combining due to register reuse.
1647 // Predecessor edges do not need to be copied from SUb to SUa since
1649 for (const SDep &Succ : SUa->Succs) {
1657 // Copy predecessor edges from SUb to SUa to avoid the SUnits tha
    [all...]
MachinePipeliner.cpp 685 /// Return true if SUb can be reached from SUa following the chain edges.
686 static bool isSuccOrder(SUnit *SUa, SUnit *SUb) {
689 Worklist.push_back(SUa);

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