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    Searched refs:SV0 (Results 1 - 2 of 2) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Transforms/InstCombine/
InstCombineSelect.cpp 2325 Value *SV0, *SV1, *SA0, *SA1;
2326 if (!match(Or0, m_OneUse(m_LogicalShift(m_Value(SV0),
2333 // Canonicalize to or(shl(SV0, SA0), lshr(SV1, SA1)).
2336 std::swap(SV0, SV1);
2353 // select ?, TVal, (or (shl SV0, SA0), (lshr SV1, SA1))
2355 // IsFShl -> TVal must be SV0 else TVal must be SV1.
2358 if ((IsFshl && TVal != SV0) || (!IsFshl && TVal != SV1))
2370 if (SV0 != SV1) {
2373 else if (!IsFshl && !llvm::isGuaranteedNotToBePoison(SV0))
2374 SV0 = Builder.CreateFreeze(SV0)
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  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
DAGCombiner.cpp 2519 const APInt &SV0 = N0.getOperand(1)->getConstantOperandAPInt(0);
2525 SDValue NewStep = DAG.getConstant(SV0 + SV1, DL, SVT);
6388 const ShuffleVectorSDNode *SV0 = cast<ShuffleVectorSDNode>(N0);
6395 int M0 = SV0->getMaskElt(i);
6418 // SV0 make the index a LHS index. If it came from SV1, make it
12657 SDValue SV0 = PeekThroughBitcast(N0->getOperand(0));
12659 if (!(SV0 && SV1))
12670 TLI.buildLegalVectorShuffle(VT, SDLoc(N), SV0, SV1, NewMask, DAG);
19633 SDValue SV0 = DAG.getUNDEF(VT), SV1 = DAG.getUNDEF(VT);
19678 if (SV0.isUndef() || SV0 == ExtVec)
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