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    Searched refs:SYS_GPCPLL_CFG_BASE (Results 1 - 2 of 2) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/subdev/clk/
gk20a.h	36 #define SYS_GPCPLL_CFG_BASE 0x00137000 37 #define GPCPLL_CFG (SYS_GPCPLL_CFG_BASE + 0) 43 #define GPCPLL_CFG2 (SYS_GPCPLL_CFG_BASE + 0xc) 47 #define GPCPLL_CFG3 (SYS_GPCPLL_CFG_BASE + 0x18) 55 #define GPCPLL_COEFF (SYS_GPCPLL_CFG_BASE + 4) 65 #define GPCPLL_NDIV_SLOWDOWN (SYS_GPCPLL_CFG_BASE + 0x1c) 78 #define SEL_VCO (SYS_GPCPLL_CFG_BASE + 0x100) 81 #define GPC2CLK_OUT (SYS_GPCPLL_CFG_BASE + 0x250)
nouveau_nvkm_subdev_clk_gm20b.c	39 #define BYPASSCTRL_SYS (SYS_GPCPLL_CFG_BASE + 0x340) 54 #define GPCPLL_DVFS0 (SYS_GPCPLL_CFG_BASE + 0x10) 64 #define GPCPLL_DVFS1 (SYS_GPCPLL_CFG_BASE + 0x14)

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