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    Searched refs:Sched (Results 1 - 25 of 25) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
HexagonDepTimingClasses.h 21 case Hexagon::Sched::tc_112d30d6:
22 case Hexagon::Sched::tc_151bf368:
23 case Hexagon::Sched::tc_1c2c7a4a:
24 case Hexagon::Sched::tc_1d41f8b7:
25 case Hexagon::Sched::tc_23708a21:
26 case Hexagon::Sched::tc_24f426ab:
27 case Hexagon::Sched::tc_2f573607:
28 case Hexagon::Sched::tc_388f9897:
29 case Hexagon::Sched::tc_3d14a17b:
30 case Hexagon::Sched::tc_3fbf1042
    [all...]
HexagonISelLowering.cpp 72 static cl::opt<bool> EnableHexSDNodeSched("enable-hexagon-sdnode-sched",
1453 setSchedulingPreference(Sched::VLIW);
1455 setSchedulingPreference(Sched::Source);
  /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
PPCHazardRecognizers.cpp 22 #define DEBUG_TYPE "pre-RA-sched"
66 if (!PredMCID || PredMCID->getSchedClass() != PPC::Sched::IIC_SprMTSPR)
95 case PPC::Sched::IIC_IntDivW:
96 case PPC::Sched::IIC_IntDivD:
97 case PPC::Sched::IIC_LdStLoadUpd:
98 case PPC::Sched::IIC_LdStLDU:
99 case PPC::Sched::IIC_LdStLFDU:
100 case PPC::Sched::IIC_LdStLFDUX:
101 case PPC::Sched::IIC_LdStLHA:
102 case PPC::Sched::IIC_LdStLHAU
    [all...]
PPCISelLowering.h 839 Sched::Preference getSchedulingPreference(SDNode *N) const override;
PPCISelLowering.cpp 1398 setSchedulingPreference(Sched::Source);
1400 setSchedulingPreference(Sched::Hybrid);
16310 Sched::Preference PPCTargetLowering::getSchedulingPreference(SDNode *N) const {
16314 return Sched::ILP;
  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
ScheduleDAG.h 290 Sched::Preference SchedulingPref = Sched::None; ///< Scheduling preference.
TargetLowering.h 95 namespace Sched {
108 } // end namespace Sched
833 Sched::Preference getSchedulingPreference() const {
840 virtual Sched::Preference getSchedulingPreference(SDNode *) const {
841 return Sched::None;
2101 void setSchedulingPreference(Sched::Preference Pref) {
2900 Sched::Preference SchedPreferenceInfo;
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
SelectionDAGISel.cpp 169 ViewSchedDAGs("view-sched-dags", cl::Hidden,
170 cl::desc("Pop up a window to show sched dags as they are processed"));
196 ISHeuristic("pre-RA-sched",
265 TLI->getSchedulingPreference() == Sched::Source)
267 if (TLI->getSchedulingPreference() == Sched::RegPressure)
269 if (TLI->getSchedulingPreference() == Sched::Hybrid)
271 if (TLI->getSchedulingPreference() == Sched::VLIW)
273 if (TLI->getSchedulingPreference() == Sched::Fast)
275 if (TLI->getSchedulingPreference() == Sched::Linearize)
277 assert(TLI->getSchedulingPreference() == Sched::ILP &
    [all...]
ScheduleDAGRRList.cpp 62 #define DEBUG_TYPE "pre-RA-sched"
93 "disable-sched-cycles", cl::Hidden, cl::init(false),
96 // Temporary sched=list-ilp flags until the heuristics are robust.
97 // Some options are also available under sched=list-hybrid.
99 "disable-sched-reg-pressure", cl::Hidden, cl::init(false),
100 cl::desc("Disable regpressure priority in sched=list-ilp"));
102 "disable-sched-live-uses", cl::Hidden, cl::init(true),
103 cl::desc("Disable live use priority in sched=list-ilp"));
105 "disable-sched-vrcycle", cl::Hidden, cl::init(false),
108 "disable-sched-physreg-join", cl::Hidden, cl::init(false)
    [all...]
ScheduleDAGSDNodes.cpp 37 #define DEBUG_TYPE "pre-RA-sched"
45 "sched-high-latency-cycles", cl::Hidden, cl::init(10),
84 SU->SchedulingPref = Sched::None;
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
R600InstrInfo.cpp 157 return (get(Opcode).getSchedClass() == R600::Sched::TransALU);
165 return (get(Opcode).getSchedClass() == R600::Sched::VecALU);
R600ISelLowering.cpp 247 setSchedulingPreference(Sched::Source);
AMDGPUISelLowering.cpp 512 setSchedulingPreference(Sched::RegPressure);
SIISelLowering.cpp 851 setSchedulingPreference(Sched::RegPressure);
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARC/
ARCISelLowering.cpp 82 setSchedulingPreference(Sched::Source);
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMISelLowering.h 577 Sched::Preference getSchedulingPreference(SDNode *N) const override;
ARMISelLowering.cpp 1532 setSchedulingPreference(Sched::RegPressure);
1534 setSchedulingPreference(Sched::Hybrid);
1866 Sched::Preference ARMTargetLowering::getSchedulingPreference(SDNode *N) const {
1869 return Sched::RegPressure;
1876 return Sched::ILP;
1880 return Sched::RegPressure;
1888 return Sched::RegPressure;
1891 return Sched::ILP;
1893 return Sched::RegPressure;
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
TargetLoweringBase.cpp 690 SchedPreferenceInfo = Sched::ILP;
  /src/external/apache2/llvm/dist/llvm/lib/Target/AVR/
AVRISelLowering.cpp 47 setSchedulingPreference(Sched::RegPressure);
  /src/external/apache2/llvm/dist/llvm/lib/Target/XCore/
XCoreISelLowering.cpp 84 setSchedulingPreference(Sched::Source);
  /src/external/apache2/llvm/dist/llvm/lib/Target/NVPTX/
NVPTXISelLowering.cpp 351 setSchedulingPreference(Sched::RegPressure);
353 setSchedulingPreference(Sched::Source);
  /src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/
WebAssemblyISelLowering.cpp 52 setSchedulingPreference(Sched::RegPressure);
  /src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/
SystemZISelLowering.cpp 124 setSchedulingPreference(Sched::RegPressure);
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86ISelLowering.cpp 132 setSchedulingPreference(Sched::ILP);
134 setSchedulingPreference(Sched::ILP);
136 setSchedulingPreference(Sched::RegPressure);
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64ISelLowering.cpp 933 setSchedulingPreference(Sched::Hybrid);

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