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    Searched refs:SchedWrites (Results 1 - 2 of 2) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/utils/TableGen/
CodeGenSchedule.h 40 /// sequences. TheDef is nonnull for explicit SchedWrites, but Sequence may or
111 /// 2) An implied class with a list of SchedWrites and SchedReads that are
116 /// SchedWrites and SchedReads per-processor. InstrClassMap should map the same
430 std::vector<CodeGenSchedRW> SchedWrites;
511 assert(Idx < SchedWrites.size() && "bad SchedWrite index");
512 assert(SchedWrites[Idx].isValid() && "invalid SchedWrite");
513 return SchedWrites[Idx];
CodeGenSchedule.cpp 185 // defined, and populate SchedReads and SchedWrites vectors. Implicit
589 SchedWrites.resize(1);
662 SchedWrites.emplace_back(SchedWrites.size(), SWDef);
670 for (CodeGenSchedRW &CGRW : SchedWrites) {
688 for (unsigned WIdx = 0, WEnd = SchedWrites.size(); WIdx != WEnd; ++WIdx) {
690 SchedWrites[WIdx].dump();
722 const std::vector<CodeGenSchedRW> &RWVec = IsRead ? SchedReads : SchedWrites;
832 std::vector<CodeGenSchedRW> &RWVec = IsRead ? SchedReads : SchedWrites;
852 std::vector<CodeGenSchedRW> &RWVec = IsRead ? SchedReads : SchedWrites;
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