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    Searched refs:Sequences (Results 1 - 6 of 6) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64A53Fix835769.cpp 9 // It works around it by inserting a nop instruction in code sequences that
198 // List of terminating instructions in matching sequences
199 std::vector<MachineInstr*> Sequences;
220 Sequences.push_back(CurrInstr);
228 LLVM_DEBUG(dbgs() << "Scan complete, " << Sequences.size()
231 // Then update the basic block, inserting nops between the detected sequences.
232 for (auto &MI : Sequences) {
  /src/external/apache2/llvm/dist/clang/include/clang/Analysis/
CloneDetection.h 179 /// `void constrain(std::vector<CloneDetector::CloneGroup> &Sequences)`
212 AllClones.reserve(Sequences.size());
213 for (const auto &C : Sequences) {
223 CloneGroup Sequences;
264 void constrain(std::vector<CloneDetector::CloneGroup> &Sequences);
275 void constrain(std::vector<CloneDetector::CloneGroup> &Sequences);
  /src/external/apache2/llvm/dist/clang/lib/Analysis/
CloneDetection.cpp 38 // If both sequences reside in different declarations, they can never contain
94 Sequences.push_back(StmtSequence(D->getBody(), D));
108 /// Returns true if and only if all sequences in \p OtherGroup are
112 // We have less sequences in the current group than we have in the other,
334 /// Returns true if both sequences are clones of each other.
352 std::vector<CloneDetector::CloneGroup> &Sequences) {
356 for (CloneDetector::CloneGroup &Group : Sequences) {
407 // Sequences is the output parameter, so we copy our result into it.
408 Sequences = Result;
412 std::vector<CloneDetector::CloneGroup> &Sequences) {
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  /src/external/apache2/llvm/dist/llvm/include/llvm/DebugInfo/DWARF/
DWARFDebugLine.h 199 /// each compilation unit may consist of multiple sequences, which are not
242 Sequences.push_back(S);
294 SequenceVector Sequences;
  /src/external/apache2/llvm/dist/llvm/lib/DebugInfo/DWARF/
DWARFDebugLine.cpp 536 Sequences.clear();
1176 // sequences. Print the final trailing new line if needed before doing so.
1194 // Sort all sequences so that address lookup will work faster.
1195 if (!Sequences.empty()) {
1196 llvm::sort(Sequences, Sequence::orderByHighPC);
1197 // Note: actually, instruction address ranges of sequences should not
1202 // rudimentary sequences for address ranges [0x0, 0xsomething).
1258 SequenceIter It = llvm::upper_bound(Sequences, Sequence,
1260 if (It == Sequences.end() || It->SectionIndex != Address.SectionIndex)
1284 if (Sequences.empty()
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  /src/external/apache2/llvm/dist/llvm/utils/TableGen/
RegisterInfoEmitter.cpp 774 SmallVector<SmallVector<MaskRolPair, 1>, 4> Sequences;
782 for (size_t s = 0, se = Sequences.size(); s != se; ++s, SIdx = NextSIdx) {
783 SmallVectorImpl<MaskRolPair> &Sequence = Sequences[s];
791 Sequences.push_back(IdxSequence);
803 for (size_t s = 0, se = Sequences.size(); s != se; ++s) {
805 const SmallVectorImpl<MaskRolPair> &Sequence = Sequences[s];
888 // List of lane masks accompanying register unit sequences.
977 // Emit the shared table of regunit lane mask sequences.

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