| /src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/ |
| LanaiISelLowering.cpp | 88 setOperationAction(ISD::SETCC, MVT::i32, Custom);
192 case ISD::SETCC:
980 return DAG.getNode(LanaiISD::SETCC, DL, Op.getValueType(), TargetCC, Flag);
1104 case LanaiISD::SETCC:
1105 return "LanaiISD::SETCC";
1259 SDValue SetCC = DAG.getSetCC(dl, MVT::i32, ShAmt, Zero, ISD::SETEQ);
1260 LoBitsForHi = DAG.getSelect(dl, MVT::i32, SetCC, Zero, LoBitsForHi);
1270 SetCC = DAG.getSetCC(dl, MVT::i32, ExtraShAmt, Zero, ISD::SETGE);
1272 DAG.getSelect(dl, MVT::i32, SetCC, HiForBigShift, HiForNormalShift);
1278 dl, MVT::i32, SetCC, DAG.getConstant(0, dl, MVT::i32), LoForNormalShift)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| MipsISelLowering.cpp | 302 // setcc operations results (slt, sgt, ...).
337 // Used by legalize types to correctly generate the setcc result.
338 // Without this, every float setcc comes with a AND/OR with the result,
341 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32);
353 setOperationAction(ISD::SETCC, MVT::f32, Custom);
354 setOperationAction(ISD::SETCC, MVT::f64, Custom);
640 // Creates and returns an FPCmp node from a setcc node.
641 // Returns Op if setcc is not a floating point comparison.
643 // must be a SETCC node
644 if (Op.getOpcode() != ISD::SETCC)
[all...] |
| MipsSEISelLowering.cpp | 105 setTargetDAGCombine(ISD::SETCC);
128 setOperationAction(ISD::SETCC, MVT::f16, Promote);
247 setOperationAction(ISD::SETCC, MVT::i32, Legal);
251 setOperationAction(ISD::SETCC, MVT::f32, Legal);
256 setOperationAction(ISD::SETCC, MVT::f64, Legal);
294 setOperationAction(ISD::SETCC, MVT::i64, Legal);
362 setOperationAction(ISD::SETCC, Ty, Legal);
399 setOperationAction(ISD::SETCC, Ty, Legal);
985 SDValue SetCC = N->getOperand(0);
987 if (SetCC.getOpcode() != MipsISD::SETCC_DSP
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/M68k/ |
| M68kISelLowering.cpp | 127 setOperationAction(ISD::SETCC, VT, Custom);
164 // M68k SETcc producess either 0x00 or 0xFF
1327 case ISD::SETCC:
1369 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
1370 // looks for this combo and may remove the "setcc" instruction if the "setcc"
1402 SDValue SetCC = DAG.getNode(M68kISD::SETCC, DL, N->getValueType(1),
1406 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Arith, SetCC);
1428 return DAG.getNode(M68kISD::SETCC, DL, MVT::i8
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| X86ISelLowering.cpp | 123 // X86 is weird. It always uses i8 for shift amounts and setcc results.
451 setOperationAction(ISD::SETCC, VT, Custom);
459 setOperationAction(ISD::SETCC, VT, Custom);
776 setOperationAction(ISD::SETCC, MVT::f128, Custom);
846 setOperationAction(ISD::SETCC, VT, Expand);
975 setOperationAction(ISD::SETCC, VT, Custom);
982 // setcc all the way to isel and prefer SETGT in some isel patterns.
1311 setOperationAction(ISD::SETCC, VT, Custom);
1318 // setcc all the way to isel and prefer SETGT in some isel patterns.
1491 setOperationAction(ISD::SETCC, VT, Custom)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| DAGCombiner.cpp | 887 // Return true if this node is a setcc, or is a select_cc
889 // equivalent to a setcc. Also, set the incoming LHS, RHS, and CC references to
894 if (N.getOpcode() == ISD::SETCC) {
925 /// Return true if this is a SetCC-equivalent operation with only one use.
1667 case ISD::SETCC: return visitSETCC(N);
2182 // Match the zext operand as a setcc of a boolean.
2183 if (Z.getOperand(0).getOpcode() != ISD::SETCC ||
2187 // Match the compare as: setcc (X & 1), 0, eq.
2188 SDValue SetCC = Z.getOperand(0);
2189 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC->getOperand(2))->get()
[all...] |
| LegalizeIntegerTypes.cpp | 81 case ISD::SETCC: Res = PromoteIntRes_SETCC(N); break;
1084 // Get the SETCC result using the canonical SETCC type.
1085 SDValue SetCC;
1090 SetCC = DAG.getNode(N->getOpcode(), dl, VTs, Opers);
1093 ReplaceValueWith(SDValue(N, 1), SetCC.getValue(1));
1095 SetCC = DAG.getNode(N->getOpcode(), dl, SVT, N->getOperand(0),
1099 return DAG.getSExtOrTrunc(SetCC, dl, NVT);
1502 case ISD::SETCC: Res = PromoteIntOp_SETCC(N, OpNo); break;
1586 /// shared among BR_CC, SELECT_CC, and SETCC handlers
[all...] |
| TargetLowering.cpp | 291 /// SELECT_CC, and SETCC handlers.
314 && "Unsupported setcc type!");
400 default: llvm_unreachable("Do not know how to soften this setcc!");
771 case ISD::SETCC: {
775 // If (1) we only need the sign-bit, (2) the setcc operands are the same
776 // width as the setcc result, and (3) the result of a setcc conforms to 0 or
777 // -1, we may be able to bypass the setcc.
1413 case ISD::SETCC: {
1417 // If (1) we only need the sign-bit, (2) the setcc operands are the sam
[all...] |
| SelectionDAGBuilder.cpp | 2070 // The operands of the setcc have to be in this block. We don't know
2364 // this as a sequence of branches instead of setcc's with and/or operations.
2455 // Build the setcc now.
3276 // If the vselect is legal, assume we want to leave this as a vector setcc +
7105 SDValue SetCC = DAG.getSetCC(DL, CCVT, VectorInduction.getValue(0),
7109 SetCC));
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| SIISelLowering.cpp | 198 setOperationAction(ISD::SETCC, MVT::i1, Promote);
199 setOperationAction(ISD::SETCC, MVT::v2i1, Expand);
200 setOperationAction(ISD::SETCC, MVT::v4i1, Expand);
201 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32);
812 setTargetDAGCombine(ISD::SETCC);
1602 // create setcc with i1 operands. We don't have instructions for i1 setcc.
1603 if (VT == MVT::i1 && Op == ISD::SETCC)
4704 SDValue SetCC = DAG.getNode(AMDGPUISD::SETCC, DL, CCVT, LHS, RHS
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| HexagonISelLoweringHVX.cpp | 183 setOperationAction(ISD::SETCC, T, Custom);
212 setOperationAction(ISD::SETCC, BoolW, Custom);
256 setOperationAction(ISD::SETCC, VecTy, Custom);
264 setOperationAction(ISD::SETCC, BoolTy, Custom);
1964 SDValue SetCC = DAG.getNode(ISD::SETCC, dl, ResTy,
1969 {SetCC, getZero(dl, MVT::i32, DAG)});
2087 case ISD::SETCC:
2118 case ISD::SETCC:
2147 case ISD::SETCC
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/ |
| SystemZISelLowering.cpp | 141 setOperationAction(ISD::SETCC, VT, Custom);
397 setOperationAction(ISD::SETCC, VT, Custom);
3700 SDValue SetCC = emitSETCC(DAG, DL, Result.getValue(1), CCValid, CCMask);
3702 SetCC = DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, SetCC);
3704 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Result, SetCC);
3766 SDValue SetCC = emitSETCC(DAG, DL, Result.getValue(1), CCValid, CCMask);
3768 SetCC = DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, SetCC);
3770 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Result, SetCC);
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.cpp | 237 // AArch64 doesn't have comparisons which set GPRs or setcc instructions, so
368 setOperationAction(ISD::SETCC, MVT::i32, Custom);
369 setOperationAction(ISD::SETCC, MVT::i64, Custom);
370 setOperationAction(ISD::SETCC, MVT::f16, Custom);
371 setOperationAction(ISD::SETCC, MVT::f32, Custom);
372 setOperationAction(ISD::SETCC, MVT::f64, Custom);
433 setOperationAction(ISD::SETCC, MVT::f128, Custom);
610 setOperationAction(ISD::SETCC, MVT::f16, Promote);
647 setOperationAction(ISD::SETCC, MVT::v4f16, Expand);
675 setOperationAction(ISD::SETCC, MVT::v8f16, Expand)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| ARMISelLowering.cpp | 169 setOperationAction(ISD::SETCC, VT, Custom);
273 setOperationAction(ISD::SETCC, VT, Custom);
338 setOperationAction(ISD::SETCC, VT, Custom);
445 setOperationAction(ISD::SETCC, VT, Custom);
834 // FIXME: Code duplication: SETCC has custom operation action, see
836 setOperationAction(ISD::SETCC, MVT::v2f64, Expand);
1358 setOperationAction(ISD::SETCC, MVT::i32, Expand);
1359 setOperationAction(ISD::SETCC, MVT::f32, Expand);
1360 setOperationAction(ISD::SETCC, MVT::f64, Expand);
1368 setOperationAction(ISD::SETCC, MVT::f16, Expand)
[all...] |
