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    Searched refs:ShOp (Results 1 - 7 of 7) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/MCTargetDesc/
ARMAddressingModes.h 112 inline unsigned getSORegOpc(ShiftOpc ShOp, unsigned Imm) {
113 return ShOp | (Imm << 3);
401 // addrmode2 := reg +/- reg shop imm
ARMMCCodeEmitter.cpp 224 /// getLdStSORegOpValue - Return encoding info for 'reg +/- reg shop imm'
1258 ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(MO2.getImm());
1259 unsigned SBits = getShiftOp(ShOp);
1296 ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(Imm);
1298 Binary |= getShiftOp(ShOp) << 5; // Shift type is bits [6:5]
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/AsmParser/
AArch64AsmParser.cpp 2058 CreateShiftExtend(AArch64_AM::ShiftExtendType ShOp, unsigned Val,
2061 Op->ShiftExtend.Type = ShOp;
2819 AArch64_AM::ShiftExtendType ShOp =
2836 if (ShOp == AArch64_AM::InvalidShiftExtend)
2845 if (ShOp == AArch64_AM::LSL || ShOp == AArch64_AM::LSR ||
2846 ShOp == AArch64_AM::ASR || ShOp == AArch64_AM::ROR ||
2847 ShOp == AArch64_AM::MSL) {
2856 AArch64Operand::CreateShiftExtend(ShOp, 0, false, S, E, getContext()))
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/Disassembler/
ARMDisassembler.cpp 1959 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl;
1962 ShOp = ARM_AM::lsl;
1965 ShOp = ARM_AM::lsr;
1968 ShOp = ARM_AM::asr;
1971 ShOp = ARM_AM::ror;
1975 if (ShOp == ARM_AM::ror && imm == 0)
1976 ShOp = ARM_AM::rrx;
1984 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp);
1986 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp);
  /src/external/apache2/llvm/dist/llvm/lib/Transforms/InstCombine/
InstCombineCompares.cpp 1549 // trunc iN (ShOp >> ShAmtC) to i[N - ShAmtC] < 0 --> ShOp < 0
1550 // trunc iN (ShOp >> ShAmtC) to i[N - ShAmtC] > -1 --> ShOp > -1
1551 Value *ShOp;
1555 match(X, m_Shr(m_Value(ShOp), m_APInt(ShAmtC))) &&
1558 ? new ICmpInst(ICmpInst::ICMP_SLT, ShOp,
1560 : new ICmpInst(ICmpInst::ICMP_SGT, ShOp,
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
DAGCombiner.cpp 4917 SDValue ShOp = N0.getOperand(1);
4918 if (LogicOpcode == ISD::XOR && !ShOp.isUndef())
4919 ShOp = tryFoldToZero(DL, TLI, VT, DAG, LegalOperations);
4922 if (N0.getOperand(1) == N1.getOperand(1) && ShOp.getNode()) {
4925 return DAG.getVectorShuffle(VT, DL, Logic, ShOp, SVN0->getMask());
4930 ShOp = N0.getOperand(0);
4931 if (LogicOpcode == ISD::XOR && !ShOp.isUndef())
4932 ShOp = tryFoldToZero(DL, TLI, VT, DAG, LegalOperations);
4935 if (N0.getOperand(0) == N1.getOperand(0) && ShOp.getNode()) {
4938 return DAG.getVectorShuffle(VT, DL, ShOp, Logic, SVN0->getMask())
    [all...]
LegalizeVectorTypes.cpp 3738 SDValue ShOp = N->getOperand(1);
3739 return DAG.getNode(N->getOpcode(), SDLoc(N), WidenVT, InOp, ShOp);

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