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    Searched refs:ShOpc (Results 1 - 8 of 8) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/MCTargetDesc/
ARMInstPrinter.cpp 52 static void printRegImmShift(raw_ostream &O, ARM_AM::ShiftOpc ShOpc,
54 if (ShOpc == ARM_AM::no_shift || (ShOpc == ARM_AM::lsl && !ShImm))
58 assert(!(ShOpc == ARM_AM::ror && !ShImm) && "Cannot have ror #0");
59 O << getShiftOpcStr(ShOpc);
61 if (ShOpc != ARM_AM::rrx) {
391 ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO3.getImm());
392 O << ", " << ARM_AM::getShiftOpcStr(ShOpc);
393 if (ShOpc == ARM_AM::rrx)
ARMMCCodeEmitter.cpp 246 unsigned getShiftOp(ARM_AM::ShiftOpc ShOpc) const {
247 switch (ShOpc) {
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/
LegalizerHelper.cpp 5561 unsigned ShOpc = IsLeft ? TargetOpcode::G_SHL : TargetOpcode::G_LSHR;
5571 ShVal = MIRBuilder.buildInstr(ShOpc, {DstTy}, {Src, ShAmt}).getReg(0);
5580 ShVal = MIRBuilder.buildInstr(ShOpc, {DstTy}, {Src, ShAmt}).getReg(0);
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMBaseInstrInfo.cpp 232 ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm);
233 unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt);
ARMISelDAGToDAG.cpp 3184 SDValue ShOpc =
3187 SDValue Ops[] = { N->getOperand(0).getOperand(0), ShOpc,
ARMISelLowering.cpp 6358 unsigned ShOpc = N->getOpcode();
6374 if (ShOpc == ISD::SRL) {
6383 } else if (ShOpc == ISD::SRA)
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
TargetLowering.cpp 6575 unsigned ShOpc = IsLeft ? ISD::SHL : ISD::SRL;
6585 ShVal = DAG.getNode(ShOpc, DL, VT, Op0, ShAmt);
6593 ShVal = DAG.getNode(ShOpc, DL, VT, Op0, ShAmt);
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86ISelLowering.cpp     [all...]

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