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    Searched refs:Shift1 (Results 1 - 4 of 4) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
AMDGPUInstructionSelector.cpp 655 bool Shift1 = mi_match(
659 if (Shift0 && Shift1) {
663 } else if (Shift1) {
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/
CombinerHelper.cpp 1877 Register Shift1 =
1887 Builder.buildInstr(MatchInfo.Logic->getOpcode(), {Dest}, {Shift1, Shift2});
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
DAGCombiner.cpp 6190 SDValue Shift1 = N1.getOperand(0);
6191 if (Shift0.getOpcode() != ISD::SHL || Shift1.getOpcode() != ISD::SRL)
6194 ConstantSDNode *ShiftAmt1 = isConstOrConstSplat(Shift1.getOperand(1));
6199 if (Shift0.getOperand(0) != Shift1.getOperand(0))
6677 // for two opposing shifts shift1 and shift2 and a value X with OpBits bits:
6679 // (or (shift1 X, Neg), (shift2 X, Pos))
6682 // in direction shift1 by Neg. The range [0, EltSize) means that we only need
6715 // (or (shift1 X, (sub 64, Pos)), (shift2 X, Pos))
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86ISelLowering.cpp     [all...]

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