| /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/MCTargetDesc/ |
| RISCVMatInt.cpp | 66 int ShiftAmount = 12 + findFirstSet((uint64_t)Hi52);
67 Hi52 = SignExtend64(Hi52 >> (ShiftAmount - 12), 64 - ShiftAmount);
71 Res.push_back(RISCVMatInt::Inst(RISCV::SLLI, ShiftAmount));
86 unsigned ShiftAmount = countLeadingZeros((uint64_t)Val);
87 Val <<= ShiftAmount;
91 Val |= maskTrailingOnes<uint64_t>(ShiftAmount);
95 TmpSeq.push_back(RISCVMatInt::Inst(RISCV::SRLI, ShiftAmount));
102 Val &= maskTrailingZeros<uint64_t>(ShiftAmount);
105 TmpSeq.push_back(RISCVMatInt::Inst(RISCV::SRLI, ShiftAmount));
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/AVR/ |
| AVRISelLowering.cpp | 312 uint64_t ShiftAmount = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
321 ShiftAmount = ShiftAmount % VT.getSizeInBits();
325 ShiftAmount = ShiftAmount % VT.getSizeInBits();
339 if (Op.getOpcode() == ISD::SHL && 4 <= ShiftAmount && ShiftAmount < 7) {
340 // Optimize LSL when 4 <= ShiftAmount <= 6.
344 ShiftAmount -= 4;
345 } else if (Op.getOpcode() == ISD::SRL && 4 <= ShiftAmount &
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/ |
| RISCVRegisterInfo.cpp | 307 uint32_t ShiftAmount = Log2_32(ZvlssegInfo->second);
308 if (ShiftAmount != 0)
311 .addImm(ShiftAmount);
|
| RISCVFrameLowering.cpp | 499 unsigned ShiftAmount = Log2(MaxAlignment);
504 .addImm(ShiftAmount);
507 .addImm(ShiftAmount);
|
| RISCVInstrInfo.cpp | 1374 uint32_t ShiftAmount = Log2_32(NumOfVReg);
1375 if (ShiftAmount == 0)
1379 .addImm(ShiftAmount);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| MipsSEISelDAGToDAG.h | 48 unsigned ShiftAmount) const;
|
| MipsTargetStreamer.h | 145 void emitDSLL(unsigned DstReg, unsigned SrcReg, int16_t ShiftAmount,
|
| MipsSEISelDAGToDAG.cpp | 283 unsigned ShiftAmount = 0) const {
286 if (isIntN(OffsetBits + ShiftAmount, CN->getSExtValue())) {
297 const Align Alignment(1ULL << ShiftAmount);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/MCTargetDesc/ |
| MipsMCCodeEmitter.h | 188 template <unsigned ShiftAmount = 0>
|
| MipsTargetStreamer.cpp | 268 int16_t ShiftAmount, SMLoc IDLoc,
270 if (ShiftAmount >= 32) {
271 emitRRI(Mips::DSLL32, DstReg, SrcReg, ShiftAmount - 32, IDLoc, STI);
275 emitRRI(Mips::DSLL, DstReg, SrcReg, ShiftAmount, IDLoc, STI);
|
| MipsMCCodeEmitter.cpp | 753 template <unsigned ShiftAmount>
764 OffBits >>= ShiftAmount;
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.cpp | 967 uint64_t ShiftAmount = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
972 if (ShiftAmount >= 8) {
992 ShiftAmount -= 8;
995 if (Opc == ISD::SRL && ShiftAmount) {
999 ShiftAmount -= 1;
1002 while (ShiftAmount--)
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/AsmParser/ |
| AArch64AsmParser.cpp | 391 unsigned ShiftAmount;
545 return ShiftedImm.ShiftAmount;
838 unsigned Shift = ShiftedImm.ShiftAmount;
1884 unsigned ShiftAmount = 0,
1892 Op->Reg.ShiftExtend.Amount = ShiftAmount;
1903 unsigned ShiftAmount = 0,
1908 auto Op = CreateReg(RegNum, Kind, S, E, Ctx, EqualsReg, ExtTy, ShiftAmount,
1948 unsigned ShiftAmount,
1953 Op->ShiftedImm.ShiftAmount = ShiftAmount;
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeVectorOps.cpp | 1043 SDValue ShiftAmount = DAG.getConstant(EltWidth - SrcEltWidth, DL, VT);
1045 DAG.getNode(ISD::SHL, DL, VT, Op, ShiftAmount),
1046 ShiftAmount);
|
| LegalizeDAG.cpp | 1584 int ShiftAmount = SignAsInt.SignBit - MagAsInt.SignBit;
1591 if (ShiftAmount > 0) {
1592 SDValue ShiftCnst = DAG.getConstant(ShiftAmount, DL, ShiftVT);
1594 } else if (ShiftAmount < 0) {
1595 SDValue ShiftCnst = DAG.getConstant(-ShiftAmount, DL, ShiftVT);
|
| TargetLowering.cpp | 6336 unsigned ShiftAmount = OuterBitSize - InnerBitSize;
6338 if (APInt::getMaxValue(ShiftAmountTy.getSizeInBits()).ult(ShiftAmount)) {
6344 SDValue Shift = DAG.getConstant(ShiftAmount, dl, ShiftAmountTy);
7337 SDValue ShiftAmount =
7340 SDValue ShiftedElt = DAG.getNode(ISD::SRL, SL, LoadVT, Load, ShiftAmount);
7422 SDValue ShiftAmount =
7425 DAG.getNode(ISD::SHL, SL, IntVT, ExtElt, ShiftAmount);
7599 SDValue ShiftAmount =
7602 SDValue Result = DAG.getNode(ISD::SHL, dl, VT, Hi, ShiftAmount);
7713 SDValue ShiftAmount = DAG.getConstant
[all...] |
| LegalizeIntegerTypes.cpp | 823 SDValue ShiftAmount = DAG.getConstant(SHLAmount, dl, SHVT);
825 DAG.getNode(ISD::SHL, dl, PromotedType, Op1Promoted, ShiftAmount);
828 DAG.getNode(ISD::SHL, dl, PromotedType, Op2Promoted, ShiftAmount);
832 return DAG.getNode(ShiftOp, dl, PromotedType, Result, ShiftAmount);
3489 SDValue ShiftAmount = DAG.getConstant(Scale % NVTSize, dl, ShiftTy);
3491 ShiftAmount);
3493 ShiftAmount);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| X86InstCombineIntrinsic.cpp | 1004 unsigned ShiftAmount = MaskC->getValue().countTrailingZeros();
1009 ShiftAmount));
1049 unsigned ShiftAmount = MaskC->getValue().countTrailingZeros();
1053 ShiftAmount));
|
| /src/external/apache2/llvm/dist/llvm/lib/Analysis/ |
| ValueTracking.cpp | 6664 unsigned ShiftAmount = Width - 1;
6666 ShiftAmount = C->countTrailingZeros();
6670 Upper = C->ashr(ShiftAmount) + 1;
6673 Lower = C->ashr(ShiftAmount);
6685 unsigned ShiftAmount = Width - 1;
6687 ShiftAmount = C->countTrailingZeros();
6688 Lower = C->lshr(ShiftAmount);
6702 unsigned ShiftAmount = C->countLeadingOnes() - 1;
6703 Lower = C->shl(ShiftAmount);
6707 unsigned ShiftAmount = C->countLeadingZeros() - 1
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| HexagonISelDAGToDAG.cpp | 1857 uint64_t ShiftAmount = V.getConstantOperandVal(1);
1858 if (ShiftAmount == Power)
1860 Ops[1] = CurDAG->getConstant(ShiftAmount - Power,
|
| /src/external/apache2/llvm/dist/llvm/lib/Transforms/InstCombine/ |
| InstCombineCasts.cpp | 498 unsigned ShiftAmount = ShiftVal ? ShiftVal->getZExtValue() : 0;
500 if ((VecWidth % DestWidth != 0) || (ShiftAmount % DestWidth != 0))
511 unsigned Elt = ShiftAmount / DestWidth;
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| AArch64ISelDAGToDAG.cpp | 2392 SDValue &Src, int &ShiftAmount,
2426 ShiftAmount = countTrailingZeros(NonZeroBits);
2427 MaskWidth = countTrailingOnes(NonZeroBits >> ShiftAmount);
2434 if (ShlImm - ShiftAmount != 0 && !BiggerPattern)
2436 Src = getLeftShift(CurDAG, Op, ShlImm - ShiftAmount);
|
| AArch64ISelLowering.cpp | 10963 uint64_t ShiftAmount = Base.getOperand(1).getConstantOperandVal(1);
10965 if (ShiftAmount == Log2_32(LoadBytes))
12539 static bool findEXTRHalf(SDValue N, SDValue &Src, uint32_t &ShiftAmount,
12551 ShiftAmount = N->getConstantOperandVal(1);
12927 uint64_t ShiftAmount = Shift.getConstantOperandVal(1);
12928 if (ShiftAmount != 1)
13576 int64_t ShiftAmount;
13586 ShiftAmount = SplatValue.getSExtValue();
13588 ShiftAmount = CVN->getSExtValue();
13627 if (IsRightShift && ShiftAmount <= -1 && ShiftAmount >= -(int)ElemBits)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/AsmParser/ |
| ARMAsmParser.cpp | 460 unsigned &ShiftAmount);
5255 const MCExpr *ShiftAmount;
5258 if (getParser().parseExpression(ShiftAmount, EndLoc)) {
5262 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
5338 const MCExpr *ShiftAmount;
5340 if (getParser().parseExpression(ShiftAmount, EndLoc)) {
5344 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
5400 const MCExpr *ShiftAmount;
5402 if (getParser().parseExpression(ShiftAmount, EndLoc)) {
5406 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/AsmParser/ |
| MipsAsmParser.cpp | 1338 template <unsigned Bits, unsigned ShiftAmount = 0>
1346 isShiftedInt<Bits, ShiftAmount>(getConstantMemOff())))
1350 return IsReloc && isShiftedInt<Bits, ShiftAmount>(Res.getConstant());
2814 unsigned ShiftAmount = FirstSet - (15 - (LastSet - FirstSet));
2815 uint16_t Bits = (ImmValue >> ShiftAmount) & 0xffff;
2817 TOut.emitRRI(Mips::DSLL, TmpReg, TmpReg, ShiftAmount, IDLoc, STI);
|
