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    Searched refs:ShiftAmtTy (Results 1 - 8 of 8) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/GlobalISel/
LegalizerHelper.h 324 LLT HalfTy, LLT ShiftAmtTy);
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/
AArch64RegisterBankInfo.cpp 607 LLT ShiftAmtTy = MRI.getType(MI.getOperand(2).getReg());
609 if (ShiftAmtTy.getSizeInBits() == 64 && SrcTy.getSizeInBits() == 32)
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
LegalizeIntegerTypes.cpp 406 EVT ShiftAmtTy = TLI.getShiftAmountTy(NOutVT, DAG.getDataLayout());
409 DAG.getConstant(ShiftAmt, dl, ShiftAmtTy));
2944 EVT ShiftAmtTy = getShiftAmountTyForConstant(NVT, TLI, DAG);
2947 DAG.getConstant(NVT.getSizeInBits() - 1, dl, ShiftAmtTy));
3026 EVT ShiftAmtTy = TLI.getShiftAmountTy(NVT, DAG.getDataLayout());
3031 DAG.getConstant(NBitWidth - 1, dl, ShiftAmtTy));
3332 EVT ShiftAmtTy = TLI.getShiftAmountTy(NVT, DAG.getDataLayout());
3333 if (APInt::getMaxValue(ShiftAmtTy.getSizeInBits()).ult(HalfBits)) {
3336 ShiftAmtTy = MVT::i32;
3338 SDValue Shift = DAG.getConstant(HalfBits, dl, ShiftAmtTy);
    [all...]
TargetLowering.cpp 1815 EVT ShiftAmtTy = VT;
1816 if (TLO.LegalTypes() && !ShiftAmtTy.isVector())
1817 ShiftAmtTy = getShiftAmountTy(ShiftAmtTy, DL);
1820 TLO.DAG.getConstant(BitWidth - ExVTBits, dl, ShiftAmtTy);
8387 EVT ShiftAmtTy = getShiftAmountTy(VT, DAG.getDataLayout());
8388 SDValue ShiftAmt = DAG.getConstant(C.logBase2(), dl, ShiftAmtTy);
DAGCombiner.cpp 4205 EVT ShiftAmtTy = getShiftAmountTy(N0.getValueType());
4206 SDValue Bits = DAG.getConstant(BitWidth, DL, ShiftAmtTy);
4208 C1 = DAG.getZExtOrTrunc(C1, DL, ShiftAmtTy);
4209 SDValue Inexact = DAG.getNode(ISD::SUB, DL, ShiftAmtTy, Bits, C1);
4215 DAG.getConstant(BitWidth - 1, DL, ShiftAmtTy));
22150 EVT ShiftAmtTy = getShiftAmountTy(N0.getValueType());
22155 SDValue ShiftAmt = DAG.getConstant(ShCt, DL, ShiftAmtTy);
22175 SDValue ShiftAmt = DAG.getConstant(ShCt, DL, ShiftAmtTy);
LegalizeVectorTypes.cpp 3793 EVT ShiftAmtTy = TLI.getShiftAmountTy(NInVT, DAG.getDataLayout());
3796 DAG.getConstant(ShiftAmt, dl, ShiftAmtTy));
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/
LegalizerHelper.cpp 4453 LLT ShiftAmtTy = MRI.getType(Amt);
4468 MI, KShiftAmt->getOperand(1).getCImm()->getValue(), HalfTy, ShiftAmtTy);
4474 auto NewBits = MIRBuilder.buildConstant(ShiftAmtTy, NewBitSize);
4480 auto AmtExcess = MIRBuilder.buildSub(ShiftAmtTy, Amt, NewBits);
4481 auto AmtLack = MIRBuilder.buildSub(ShiftAmtTy, NewBits, Amt);
4483 auto Zero = MIRBuilder.buildConstant(ShiftAmtTy, 0);
4523 auto ShiftAmt = MIRBuilder.buildConstant(ShiftAmtTy, NewBitSize - 1);
CombinerHelper.cpp 1947 LLT ShiftAmtTy = getTargetLowering().getPreferredShiftAmountTy(SrcTy);
1948 if (!isLegalOrBeforeLegalizer({TargetOpcode::G_SHL, {SrcTy, ShiftAmtTy}}))

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