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    Searched refs:ShiftOpc (Results 1 - 13 of 13) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/MCTargetDesc/
ARMAddressingModes.h 27 enum ShiftOpc {
44 inline const char *getShiftOpcStr(ShiftOpc Op) {
56 inline unsigned getShiftOpcEncoding(ShiftOpc Op) {
112 inline unsigned getSORegOpc(ShiftOpc ShOp, unsigned Imm) {
116 inline ShiftOpc getSORegShOp(unsigned Op) { return (ShiftOpc)(Op & 7); }
413 inline unsigned getAM2Opc(AddrOpc Opc, unsigned Imm12, ShiftOpc SO,
425 inline ShiftOpc getAM2ShiftOpc(unsigned AM2Opc) {
426 return (ShiftOpc)((AM2Opc >> 13) & 7);
ARMMCCodeEmitter.cpp 246 unsigned getShiftOp(ARM_AM::ShiftOpc ShOpc) const {
255 llvm_unreachable("Invalid ShiftOpc!");
1258 ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(MO2.getImm());
1296 ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(Imm);
1511 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm());
1556 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO1.getImm());
1665 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO1.getImm());
ARMInstPrinter.cpp 52 static void printRegImmShift(raw_ostream &O, ARM_AM::ShiftOpc ShOpc,
391 ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO3.getImm());
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMSelectionDAGInfo.h 23 static inline ShiftOpc getShiftOpcForNode(unsigned Opcode) {
ARMInstructionSelector.cpp 62 bool selectShift(unsigned ShiftOpc, MachineInstrBuilder &MIB) const;
804 bool ARMInstructionSelector::selectShift(unsigned ShiftOpc,
808 MIB.addImm(ShiftOpc);
1060 return selectShift(ARM_AM::ShiftOpc::lsr, MIB);
1062 return selectShift(ARM_AM::ShiftOpc::asr, MIB);
1064 return selectShift(ARM_AM::ShiftOpc::lsl, MIB);
ARMFastISel.cpp 182 bool SelectShift(const Instruction *I, ARM_AM::ShiftOpc ShiftTy);
2690 ARM_AM::ShiftOpc Shift = (ARM_AM::ShiftOpc) ITP->Shift;
2717 ARM_AM::ShiftOpc ShiftAM = isLsl ? ARM_AM::lsl : Shift;
2763 ARM_AM::ShiftOpc ShiftTy) {
ARMISelDAGToDAG.cpp 83 ARM_AM::ShiftOpc ShOpcVal, unsigned ShAmt);
527 ARM_AM::ShiftOpc ShOpcVal,
600 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOpcode());
624 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOpcode());
746 ARM_AM::ShiftOpc ShOpcVal =
826 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOpcode());
1495 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(OffReg.getOpcode());
3183 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(ISD::SRL);
ARMBaseInstrInfo.cpp 232 ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm);
ARMISelLowering.cpp 17830 ARM_AM::ShiftOpc ShOpcVal=
  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
HexagonSplitDouble.cpp 800 unsigned ShiftOpc = Left ? S2_asl_i_r
838 BuildMI(B, MI, DL, TII->get(ShiftOpc), (Left ? LoR : TmpR))
855 BuildMI(B, MI, DL, TII->get(ShiftOpc), HiR)
884 BuildMI(B, MI, DL, TII->get(ShiftOpc), (Left ? HiR : LoR))
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/AsmParser/
ARMAsmParser.cpp 459 bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType,
852 ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg
862 ARM_AM::ShiftOpc ShiftTy;
872 ARM_AM::ShiftOpc ShiftTy;
879 ARM_AM::ShiftOpc ShiftTy;
3639 CreateShiftedRegister(ARM_AM::ShiftOpc ShTy, unsigned SrcReg,
3653 CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy, unsigned SrcReg,
3804 ARM_AM::ShiftOpc ShiftType, unsigned ShiftImm, unsigned Alignment,
3821 CreatePostIdxReg(unsigned RegNum, bool isAdd, ARM_AM::ShiftOpc ShiftTy,
4141 ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/Disassembler/
ARMDisassembler.cpp 1482 ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
1521 ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
1914 ARM_AM::ShiftOpc Opc = ARM_AM::lsl;
1959 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl;
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64ISelDAGToDAG.cpp 2677 unsigned ShiftOpc = (VT == MVT::i32) ? AArch64::UBFMWri : AArch64::UBFMXri;
2679 ShiftOpc, DL, VT, Src, CurDAG->getTargetConstant(LSB, DL, VT),

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