HomeSort by: relevance | last modified time | path
    Searched refs:ShiftReg (Results 1 - 6 of 6) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/MSP430/
MSP430ISelLowering.cpp 1499 Register ShiftReg = RI.createVirtualRegister(RC);
1515 // ShiftReg = phi [%SrcReg, BB], [%ShiftReg2, LoopBB]
1517 // ShiftReg2 = shift ShiftReg
1519 BuildMI(LoopBB, dl, TII.get(MSP430::PHI), ShiftReg)
1530 .addReg(ShiftReg)
1531 .addReg(ShiftReg);
1534 .addReg(ShiftReg);
1542 // DestReg = phi [%SrcReg, BB], [%ShiftReg, LoopBB]
  /src/external/apache2/llvm/dist/llvm/lib/Target/AVR/
AVRISelLowering.cpp 1586 Register ShiftReg = RI.createVirtualRegister(RC);
1597 // ShiftReg2 = shift ShiftReg
1598 auto ShiftMI = BuildMI(LoopBB, dl, TII.get(Opc), ShiftReg2).addReg(ShiftReg);
1600 ShiftMI.addReg(ShiftReg);
1603 // ShiftReg = phi [%SrcReg, BB], [%ShiftReg2, LoopBB]
1605 // DestReg = phi [%SrcReg, BB], [%ShiftReg, LoopBB]
1608 BuildMI(CheckBB, dl, TII.get(AVR::PHI), ShiftReg)
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/
AArch64InstructionSelector.cpp 1852 Register ShiftReg = I.getOperand(2).getReg();
1853 const LLT ShiftTy = MRI.getType(ShiftReg);
1860 auto *AmtMI = MRI.getVRegDef(ShiftReg);
1865 .addReg(ShiftReg, 0, AArch64::sub_32);
5736 Register ShiftReg = ShiftLHS.getReg();
5738 unsigned NumBits = MRI.getType(ShiftReg).getSizeInBits();
5742 return {{[=](MachineInstrBuilder &MIB) { MIB.addUse(ShiftReg); },
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/AsmParser/
ARMAsmParser.cpp 874 unsigned ShiftReg;
1389 RegShiftedReg.ShiftReg);
2549 Inst.addOperand(MCOperand::createReg(RegShiftedReg.ShiftReg));
3640 unsigned ShiftReg, unsigned ShiftImm, SMLoc S,
3645 Op->RegShiftedReg.ShiftReg = ShiftReg;
3988 << RegName(RegShiftedReg.ShiftReg) << ">";
4166 int ShiftReg = 0;
4171 ShiftReg = SrcReg;
4206 ShiftReg = tryParseRegister()
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
PPCISelLowering.cpp 11218 Register ShiftReg =
11274 BuildMI(BB, dl, TII->get(PPC::XORI), ShiftReg)
11288 BuildMI(BB, dl, TII->get(PPC::SLW), Incr2Reg).addReg(incr).addReg(ShiftReg);
11299 .addReg(ShiftReg);
11326 .addReg(ShiftReg);
11368 .addReg(ShiftReg);
12224 Register ShiftReg =
12288 BuildMI(BB, dl, TII->get(PPC::XORI), ShiftReg)
12304 .addReg(ShiftReg);
12307 .addReg(ShiftReg);
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64FastISel.cpp 3684 unsigned ShiftReg = emitLSR_ri(MVT::i64, MVT::i64, MulReg, 32);
3686 ShiftReg = fastEmitInst_extractsubreg(VT, ShiftReg, AArch64::sub_32);
3687 emitSubs_rs(VT, ShiftReg, MulReg, AArch64_AM::ASR, 31,

Completed in 36 milliseconds