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    Searched refs:ShiftWidth (Results 1 - 5 of 5) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/
RISCVISelDAGToDAG.h 49 bool selectShiftMask(SDValue N, unsigned ShiftWidth, SDValue &ShAmt);
RISCVISelDAGToDAG.cpp 1220 bool RISCVDAGToDAGISel::selectShiftMask(SDValue N, unsigned ShiftWidth,
1230 assert(isPowerOf2_32(ShiftWidth) && "Unexpected max shift amount!");
1231 APInt ShMask(AndMask.getBitWidth(), ShiftWidth - 1);
  /src/external/apache2/llvm/dist/llvm/include/llvm/IR/
PatternMatch.h 2335 unsigned ShiftWidth = TypeSize - 1;
2348 auto LHS = m_AShr(m_Value(OpL), m_SpecificInt(ShiftWidth));
2349 auto RHS = m_LShr(m_Neg(m_Value(OpR)), m_SpecificInt(ShiftWidth));
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/AsmParser/
AArch64AsmParser.cpp 1140 AArch64_AM::ShiftExtendType ShiftExtendTy, int ShiftWidth,
1150 bool MatchShift = getShiftExtendAmount() == Log2_32(ShiftWidth / 8);
1153 !ShiftWidthAlwaysSame && hasShiftExtendAmount() && ShiftWidth == 8)
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
AMDGPURegisterBankInfo.cpp 1571 auto ShiftWidth = B.buildShl(S32, WidthReg, B.buildConstant(S32, 16));
1576 auto MergedInputs = B.buildOr(S32, ClampOffset, ShiftWidth);

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