HomeSort by: relevance | last modified time | path
    Searched refs:Shifted (Results 1 - 15 of 15) sorted by relevancy

  /src/external/apache2/llvm/dist/clang/lib/Tooling/ASTDiff/
ASTDiff.cpp 150 int findPositionInParent(NodeId Id, bool Shifted = false) const;
339 int SyntaxTree::Impl::findPositionInParent(NodeId Id, bool Shifted) const {
346 if (Shifted)
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMFrameLowering.cpp 2334 unsigned Shifted = 0;
2341 Shifted += 2;
2350 if (Shifted > 24)
2351 Value = Value >> (Shifted - 24);
2353 Value = Value << (24 - Shifted);
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86InstCombineIntrinsic.cpp 1002 // describes a subset of the input bits shifted to the appropriate
1007 Value *Shifted = IC.Builder.CreateLShr(Masked,
1010 return IC.replaceInstUsesWith(II, Shifted);
1047 // describes a subset of the input bits shifted to the appropriate
1051 Value *Shifted = IC.Builder.CreateShl(Input,
1054 Value *Masked = IC.Builder.CreateAnd(Shifted, II.getArgOperand(1));
X86ISelLowering.cpp 7842 // Clear mask to all zeros and insert the shifted byte indices.
12823 /// right with zeroable elements 'shifted in'. It handles both the strictly
12888 // and that the shifted in elements are all zeroable.
14274 NewMask[V2Index] = 0; // We shifted the V2 element into V2[0].
24785 // All shifted in bits must be the same so use 0.
    [all...]
  /src/external/gpl3/gdb/dist/sim/ppc/
powerpc.igen 2524 0.15,6.RT,11.RA,16.SI:D:::Add Immediate Shifted
2966 0.29,6.RS,11.RA,16.UI:D:::AND Immediate Shifted
2985 0.25,6.RS,11.RA,16.UI:D:::OR Immediate Shifted
3003 0.27,6.RS,11.RA,16.UI:D:::XOR Immediate Shifted
3259 signed_word shifted;
3261 shifted = (source << n);
3263 shifted = 0;
3264 *rA = shifted;
3265 CR0_COMPARE(shifted, 0, Rc);
3267 ("n=%d, source=0x%lx, shifted=0x%lx\n"
    [all...]
  /src/external/gpl3/gdb.old/dist/sim/ppc/
powerpc.igen 2524 0.15,6.RT,11.RA,16.SI:D:::Add Immediate Shifted
2966 0.29,6.RS,11.RA,16.UI:D:::AND Immediate Shifted
2985 0.25,6.RS,11.RA,16.UI:D:::OR Immediate Shifted
3003 0.27,6.RS,11.RA,16.UI:D:::XOR Immediate Shifted
3259 signed_word shifted;
3261 shifted = (source << n);
3263 shifted = 0;
3264 *rA = shifted;
3265 CR0_COMPARE(shifted, 0, Rc);
3267 ("n=%d, source=0x%lx, shifted=0x%lx\n"
    [all...]
  /src/external/apache2/llvm/dist/clang/lib/Format/
Format.cpp 2742 auto Shifted = tooling::Replacement(FileName, NewOffset, 0,
2744 Result = Result.merge(tooling::Replacements(Shifted));
  /src/external/apache2/llvm/dist/llvm/lib/Analysis/
ScalarEvolution.cpp 5232 // We can generalize this saying that i is the shifted value of BEValue
5235 const SCEV *Shifted = SCEVShiftRewriter::rewrite(BEValue, L, *this);
5236 const SCEV *Start = SCEVInitRewriter::rewrite(Shifted, L, *this, false);
5237 if (Shifted != getCouldNotCompute() &&
5245 ValueExprMap[SCEVCallbackVH(PN, this)] = Shifted;
5246 return Shifted;
5759 // Iff no bits are shifted out, value increases on every shift.
8028 // Recognize a "shift recurrence" either of the form %iv or of %iv.shifted in
8031 // %iv = phi i32 [ %iv.shifted, %loop ], [ %val, %preheader ]
8032 // %iv.shifted = lshr i32 %iv, <positive constant
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/
LegalizerHelper.cpp 2977 auto Shifted = MIRBuilder.buildAShr(Ty, Res, ShiftAmt);
2978 MIRBuilder.buildICmp(CmpInst::ICMP_NE, Overflow, HiPart, Shifted);
6698 // Low byte shifted left to place of high byte: (Src & Mask) << ShiftAmt.
6702 // High byte shifted right to place of low byte: (Src >> ShiftAmt) & Mask.
6796 auto Shifted = MIRBuilder.buildInstr(ShiftOp, {WideTy}, {Mul, ShiftAmt});
6797 MIRBuilder.buildTrunc(Result, Shifted);
  /src/external/gpl3/gcc.old/dist/libgcc/config/avr/
lib1funcs.S 1859 1: ;; Compare shifted Devidend against Divisor
1875 ;; Shifted 64 Bits: A7 has traveled to C7
1892 ;; Compare shifted Dividend against Divisor
1900 ;; Divisor is greater than shifted Dividen: We can shift the Dividend
  /src/external/gpl3/gcc/dist/libgcc/config/avr/
lib1funcs.S 1864 1: ;; Compare shifted Devidend against Divisor
1880 ;; Shifted 64 Bits: A7 has traveled to C7
1897 ;; Compare shifted Dividend against Divisor
1905 ;; Divisor is greater than shifted Dividen: We can shift the Dividend
  /src/external/apache2/llvm/dist/llvm/lib/Transforms/Utils/
SimplifyCFG.cpp 6056 Value *Shifted = Builder.CreateLShr(TableMask, MaskIndex, "switch.shifted");
6058 Shifted, Type::getInt1Ty(Mod.getContext()), "switch.lobit");
6190 // Now we have signed numbers that have been shifted so that, given enough
6221 // shift and puts the shifted-off bits in the uppermost bits. If any of these
  /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/
RISCVISelLowering.cpp 4523 SDValue Shifted = DAG.getNode(ISD::SRL, DL, XLenVT,
4525 SDValue Masked = DAG.getNode(ISD::AND, DL, XLenVT, Shifted,
4553 SDValue Shifted = DAG.getNode(ISD::SRL, DL, XLenVT,
4555 RMValue = DAG.getNode(ISD::AND, DL, XLenVT, Shifted,
5150 // The expected mask is shifted left when the AND is found around SHL
5162 // The expected mask is now in fact shifted left for SRL, so reverse the
5168 // Use a default shifted mask of all-ones if there's no AND, truncated
5201 // patterns. They may be shifted left in certain circumstances.
5307 // patterns. They may be shifted left in certain circumstances.
  /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
PPCISelLowering.cpp 7251 // Every load here needs to be shifted, otherwise a full register load
9229 // Figure out what shift amount will be used by altivec if shifted by i in
11314 // For unsigned comparisons, we can directly compare the shifted values.
12935 auto Shifted = DAG.getNode(ISD::SRL, DL, MVT::i64, SubNode,
12937 auto Final = Shifted;
12941 Final = DAG.getNode(ISD::XOR, DL, MVT::i64, Shifted,
14763 // it need to be shifted to the right side before STBRX.
15765 case 'L': // "L" is a signed 16-bit constant shifted left 16 bits.
16189 // 2. If the multiplier after shifted fits 16 bits, an extra shift
17298 // zero or load-immediate-shifted and the displacement will b
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
DAGCombiner.cpp 585 SDValue MatchRotatePosNeg(SDValue Shifted, SDValue Pos, SDValue Neg,
2207 /// Try to fold a 'not' shifted sign-bit with add/sub with constant operand into
6019 // Also allow 0xFFFF since the bits will be shifted out. This is needed
6094 // In case demanded bits didn't clear the bits that will be shifted out.
6798 // shifts of Shifted. If Neg == <operand size> - Pos then the OR reduces
6799 // to both (PosOpcode Shifted, Pos) and (NegOpcode Shifted, Neg), with the
6802 SDValue DAGCombiner::MatchRotatePosNeg(SDValue Shifted, SDValue Pos,
6813 EVT VT = Shifted.getValueType();
6817 return DAG.getNode(HasPos ? PosOpcode : NegOpcode, DL, VT, Shifted,
    [all...]

Completed in 135 milliseconds