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    Searched refs:ShiftedVal (Results 1 - 4 of 4) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/
AArch64PostLegalizerCombiner.cpp 212 auto ShiftedVal = B.buildShl(Ty, LHS, Shift);
214 Register AddSubLHS = ShiftValUseIsLHS ? ShiftedVal.getReg(0) : LHS;
215 Register AddSubRHS = ShiftValUseIsLHS ? LHS : ShiftedVal.getReg(0);
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86ISelDAGToDAG.cpp 3973 auto CanShrinkImmediate = [&](int64_t &ShiftedVal) {
3977 ShiftedVal = (uint64_t)Val >> ShAmt;
3978 if (NVT == MVT::i64 && !isUInt<32>(Val) && isUInt<32>(ShiftedVal))
3981 if (ShiftedVal == UINT8_MAX || ShiftedVal == UINT16_MAX)
3984 ShiftedVal = Val >> ShAmt;
3985 if ((!isInt<8>(Val) && isInt<8>(ShiftedVal)) ||
3986 (!isInt<32>(Val) && isInt<32>(ShiftedVal)))
3990 ShiftedVal = (uint64_t)Val >> ShAmt;
3991 if (NVT == MVT::i64 && !isUInt<32>(Val) && isUInt<32>(ShiftedVal))
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/AsmParser/
AArch64AsmParser.cpp 867 if (auto ShiftedVal = getShiftedVal<12>())
868 return ShiftedVal->first >= 0 && ShiftedVal->first <= 0xfff;
880 if (auto ShiftedVal = getShiftedVal<12>())
881 return ShiftedVal->first < 0 && -ShiftedVal->first <= 0xfff;
1598 if (auto ShiftedVal = getShiftedVal<Shift>()) {
1599 Inst.addOperand(MCOperand::createImm(ShiftedVal->first));
1600 Inst.addOperand(MCOperand::createImm(ShiftedVal->second));
1613 if (auto ShiftedVal = getShiftedVal<Shift>())
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64ISelLowering.cpp 12290 SDValue ShiftedVal = DAG.getNode(ISD::SHL, DL, VT, N0,
12293 SDValue AddSubN0 = ShiftValUseIsN0 ? ShiftedVal : N0;
12294 SDValue AddSubN1 = ShiftValUseIsN0 ? N0 : ShiftedVal;

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