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    Searched refs:Shl (Results 1 - 25 of 110) sorted by relevancy

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  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
HexagonOptimizeSZextends.cpp 101 // %sext233 = shl i32 %34, 16
116 Instruction *Shl = dyn_cast<Instruction>(Ashr->getOperand(0));
117 if (!(Shl && Shl->getOpcode() == Instruction::Shl))
119 Value *Intr = Shl->getOperand(0);
120 Value *ShlOp1 = Shl->getOperand(1);
126 // The first operand of Shl comes from an intrinsic.
  /src/external/apache2/llvm/dist/llvm/lib/IR/
ReplaceConstant.cpp 42 case Instruction::Shl:
Instruction.cpp 145 case Instruction::Shl:
385 case Shl: return "shl";
  /src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/
WebAssemblyTargetTransformInfo.cpp 68 case Instruction::Shl:
  /src/external/apache2/llvm/dist/llvm/include/llvm/IR/
Operator.h 64 /// Mul, and Shl. It does not include SDiv, despite that operator having the
104 I->getOpcode() == Instruction::Shl;
110 CE->getOpcode() == Instruction::Shl;
439 : public ConcreteOperator<OverflowingBinaryOperator, Instruction::Shl> {
Instruction.h 196 return Opcode >= Shl && Opcode <= AShr;
201 return getOpcode() == Shl || getOpcode() == LShr;
  /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/
RISCVTargetTransformInfo.cpp 63 case Instruction::Shl:
  /src/external/apache2/llvm/dist/llvm/lib/Transforms/Scalar/
Reassociate.cpp 924 // consists of an `or`/`shl`/`zext`/`load` nodes only. Note that we don't
958 case Instruction::Shl:
960 // `shl`/`zext` nodes are fine, just recurse into their base operand.
984 Instruction::Shl})
1072 static BinaryOperator *ConvertShiftToMul(Instruction *Shl) {
1073 Constant *MulCst = ConstantInt::get(Shl->getType(), 1);
1074 auto *SA = cast<ConstantInt>(Shl->getOperand(1));
1078 BinaryOperator::CreateMul(Shl->getOperand(0), MulCst, "", Shl);
1079 Shl->setOperand(0, UndefValue::get(Shl->getType())); // Drop use of op
    [all...]
SpeculativeExecution.cpp 222 case Instruction::Shl:
  /src/external/apache2/llvm/dist/llvm/lib/Transforms/InstCombine/
InstCombineShifts.cpp 149 if (ShiftOpcode == Instruction::BinaryOps::Shl) {
188 assert(OuterShift->getOpcode() == Instruction::BinaryOps::Shl &&
189 "The input must be 'shl'!");
442 // shl (shl X, C1), C2 --> shl X, C1 + C2
444 bool IsInnerShl = InnerShift->getOpcode() == Instruction::Shl;
449 // lshr (shl X, C), C --> and X, C'
450 // shl (lshr X, C), C --> and X, C'
455 // lshr (shl X, C1), C2 --> and (shl X, C1 - C2), C
    [all...]
InstCombineMulDivRem.cpp 85 if (I->getOpcode() == Instruction::Shl && !I->hasNoUnsignedWrap()) {
176 Constant *Shl = ConstantExpr::getShl(C1, C2);
178 BinaryOperator *BO = BinaryOperator::CreateMul(NewOp, Shl);
182 Shl->isNotMinSignedValue())
190 BinaryOperator *Shl = BinaryOperator::CreateShl(NewOp, NewCst);
193 Shl->setHasNoUnsignedWrap();
197 Shl->setHasNoSignedWrap();
200 return Shl;
InstCombineCompares.cpp 1172 /// Handle "(icmp eq/ne (shl AP2, A), AP1)" ->
1202 if (Shift > 0 && AP2.shl(Shift) == AP1)
1649 bool IsShl = ShiftOpcode == Instruction::Shl;
1654 if (ShiftOpcode == Instruction::Shl) {
1664 AnyCmpCstBitsShiftedOut = NewCmpCst.shl(*C3) != C1;
1670 NewCmpCst = C1.shl(*C3);
1671 NewAndCst = C2.shl(*C3);
1679 NewCmpCst = C1.shl(*C3);
1680 NewAndCst = C2.shl(*C3);
1789 // (icmp pred (and A, (or (shl 1, B), 1), 0)
    [all...]
InstCombineVectorOps.cpp 1501 case Instruction::Shl:
1570 case Instruction::Shl:
1660 case Instruction::Shl:
1769 case Instruction::Shl: {
1770 // shl X, C --> mul X, (1 << C)
1925 if (Opc0 == Instruction::Shl || Opc1 == Instruction::Shl)
InstCombineNegator.cpp 351 case Instruction::Shl: {
352 // `shl` is negatible if the first operand is negatible.
355 // Otherwise, `shl %x, C` can be interpreted as `mul %x, 1<<C`.
InstCombineSimplifyDemanded.cpp 530 case Instruction::Shl: {
594 APInt DemandedMaskIn(DemandedMask.shl(ShiftAmt));
635 APInt DemandedMaskIn(DemandedMask.shl(ShiftAmt));
820 APInt DemandedMaskRHS(DemandedMask.shl(BitWidth - ShiftAmt));
825 Known.Zero = LHSKnown.Zero.shl(ShiftAmt) |
827 Known.One = LHSKnown.One.shl(ShiftAmt) |
1006 Instruction *Shr, const APInt &ShrOp1, Instruction *Shl,
1050 BinaryOperator *Orig = cast<BinaryOperator>(Shl);
1061 return InsertNewInstWith(New, *Shl);
  /src/external/apache2/llvm/dist/llvm/lib/FuzzMutate/
Operations.cpp 26 Ops.push_back(binOpDescriptor(1, Instruction::Shl));
104 case Instruction::Shl:
IRMutator.cpp 212 case Instruction::Shl:
  /src/external/apache2/llvm/dist/clang/include/clang/AST/
StmtVisitor.h 128 BINOP_FALLBACK(Add) BINOP_FALLBACK(Sub) BINOP_FALLBACK(Shl)
  /src/external/apache2/llvm/dist/llvm/include/llvm/MC/
MCExpr.h 501 Shl, ///< Shift left.
595 return create(Shl, LHS, RHS, Ctx);
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
MVELaneInterleavingPass.cpp 232 case Instruction::Shl:
  /src/external/apache2/llvm/dist/llvm/lib/Transforms/Instrumentation/
PoisonChecking.cpp 173 case Instruction::Shl: {
354 - NSW/NUW flags on shl produce poison
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
AMDGPUInstCombineIntrinsic.cpp 451 Value *Shl = IC.Builder.CreateShl(Src, IntSize - Offset - Width);
452 Value *RightShift = Signed ? IC.Builder.CreateAShr(Shl, IntSize - Width)
453 : IC.Builder.CreateLShr(Shl, IntSize - Width);
  /src/external/apache2/llvm/dist/llvm/include/llvm/Transforms/InstCombine/
InstCombiner.h 329 case Instruction::Shl: // 0 << X = 0
  /src/external/apache2/llvm/dist/llvm/lib/MC/
MCExpr.cpp 154 case MCBinaryExpr::Shl: OS << "<<"; break;
977 case MCBinaryExpr::Shl: Result = uint64_t(LHS) << uint64_t(RHS); break;
  /src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/
SystemZTargetTransformInfo.cpp 158 case Instruction::Shl:
491 if (Opcode == Instruction::Shl || Opcode == Instruction::LShr ||

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