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    Searched refs:SignBit (Results 1 - 11 of 11) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/include/llvm/DebugInfo/DWARF/
DWARFExpression.h 49 SignBit = 0x80,
50 SignedSize1 = SignBit | Size1,
51 SignedSize2 = SignBit | Size2,
52 SignedSize4 = SignBit | Size4,
53 SignedSize8 = SignBit | Size8,
54 SignedSizeLEB = SignBit | SizeLEB,
  /src/external/apache2/llvm/dist/clang/lib/AST/Interp/
Integral.h 144 const T SignBit = T(1) << (TruncBits - 1);
146 return Integral((V & BitMask) | (Signed && (V & SignBit) ? ExtMask : 0));
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
LegalizeFloatTypes.cpp 321 SDValue SignBit = DAG.getNode(
325 SignBit = DAG.getNode(ISD::AND, dl, RVT, RHS, SignBit);
330 SignBit =
331 DAG.getNode(ISD::SRL, dl, RVT, SignBit,
333 TLI.getShiftAmountTy(SignBit.getValueType(),
335 SignBit = DAG.getNode(ISD::TRUNCATE, dl, LVT, SignBit);
337 SignBit = DAG.getNode(ISD::ANY_EXTEND, dl, LVT, SignBit);
    [all...]
LegalizeDAG.cpp 71 uint8_t SignBit;
1496 State.SignBit = NumBits - 1;
1532 State.SignBit = 7;
1561 SDValue SignBit = DAG.getNode(ISD::AND, DL, IntVT, SignAsInt.IntValue,
1570 SDValue Cond = DAG.getSetCC(DL, getSetCCResultType(IntVT), SignBit,
1583 // Get the signbit at the right position for MagAsInt.
1584 int ShiftAmount = SignAsInt.SignBit - MagAsInt.SignBit;
1586 if (SignBit.getScalarValueSizeInBits() <
1588 SignBit = DAG.getNode(ISD::ZERO_EXTEND, DL, MagVT, SignBit)
    [all...]
DAGCombiner.cpp 12501 // fold (bitconvert (fneg x)) -> (xor (bitconvert x), signbit)
12502 // fold (bitconvert (fabs x)) -> (and (bitconvert x), (not signbit))
12506 // flipbit = signbit
12510 // flipbit = (and (extract_element (bitcast x), 0), signbit)
12523 SDValue SignBit = DAG.getConstant(
12527 FlipBit = SignBit;
12536 FlipBit = DAG.getNode(ISD::AND, SDLoc(N0), MVT::i64, Hi, SignBit);
12544 APInt SignBit = APInt::getSignMask(VT.getSizeInBits());
12547 NewConv, DAG.getConstant(SignBit, DL, VT));
12550 NewConv, DAG.getConstant(~SignBit, DL, VT))
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/DebugInfo/DWARF/
DWARFExpression.cpp 132 unsigned Signed = Size & Operation::SignBit;
137 switch (Size & ~Operation::SignBit) {
284 unsigned Signed = Size & Operation::SignBit;
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
AMDGPUISelLowering.cpp 2173 SDValue SignBit = DAG.getNode(ISD::AND, SL, MVT::i32, Hi, SignBitMask);
2176 SDValue SignBit64 = DAG.getBuildVector(MVT::v2i32, SL, {Zero, SignBit});
2426 const SDValue SignBit = DAG.getConstant(63, SL, MVT::i64);
2427 S = DAG.getNode(ISD::SRA, SL, MVT::i64, L, SignBit);
AMDGPULegalizerInfo.cpp 1996 auto SignBit = B.buildAnd(S32, Hi, SignBitMask);
2003 auto SignBit64 = B.buildMerge(S64, {Zero32, SignBit});
  /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/
RISCVISelLowering.cpp 5543 // fold (bitconvert (fneg x)) -> (xor (bitconvert x), signbit)
5544 // fold (bitconvert (fabs x)) -> (and (bitconvert x), (not signbit))
5553 APInt SignBit = APInt::getSignMask(32);
5556 DAG.getConstant(SignBit, DL, MVT::i32));
5561 DAG.getConstant(~SignBit, DL, MVT::i32));
5717 // fold (bitconvert (fneg x)) -> (xor (bitconvert x), signbit)
5718 // fold (bitconvert (fabs x)) -> (and (bitconvert x), (not signbit))
5724 APInt SignBit = APInt::getSignMask(32).sext(64);
5727 DAG.getConstant(SignBit, DL, MVT::i64));
5731 DAG.getConstant(~SignBit, DL, MVT::i64))
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/
LegalizerHelper.cpp 360 // In the sign extend padding case, re-use the first all-signbit merge.
5707 auto SignBit = MIRBuilder.buildConstant(S64, 63);
5708 auto S = MIRBuilder.buildAShr(S64, L, SignBit);
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86ISelLowering.cpp 21980 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, LogicVT, Sign, SignMask);
21998 SDValue Or = DAG.getNode(X86ISD::FOR, dl, LogicVT, MagBits, SignBit);
    [all...]

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