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    Searched refs:Size0 (Results 1 - 3 of 3) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
HexagonSubtarget.cpp 348 unsigned Size0;
349 MachineOperand *BaseOp0 = HII.getBaseAndOffset(L0, Offset0, Size0);
351 if (BaseOp0 == nullptr || !BaseOp0->isReg() || Size0 >= 32)
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
AMDGPURegisterBankInfo.cpp 3899 unsigned Size0 = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
3900 OpdsMapping[0] = AMDGPU::getValueMapping(ResultBank, Size0);
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
DAGCombiner.cpp 22811 auto &Size0 = MUC0.NumBytes;
22814 Size0.hasValue() && Size1.hasValue() && *Size0 == *Size1 &&
22815 OrigAlignment0 > *Size0 && SrcValOffset0 % *Size0 == 0 &&
22822 if ((OffAlign0 + *Size0) <= OffAlign1 || (OffAlign1 + *Size1) <= OffAlign0)
22836 Size0.hasValue() && Size1.hasValue()) {
22839 int64_t Overlap0 = *Size0 + SrcValOffset0 - MinOffset;

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