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  /src/external/gpl3/gdb.old/dist/sim/arm/
armsupp.c 162 /* Get an SPSR from the specified mode. */
172 return state->Spsr[bank];
175 /* This routine does a write to an SPSR. */
183 state->Spsr[bank] = value;
186 /* This routine does a write to the current SPSR, given an MSR instruction. */
194 SETPSR_C (state->Spsr[state->Bank], rhs);
196 SETPSR_X (state->Spsr[state->Bank], rhs);
198 SETPSR_S (state->Spsr[state->Bank], rhs);
200 SETPSR_F (state->Spsr[state->Bank], rhs);
arminit.c 96 state->Spsr[i] = 0;
armdefs.h 84 ARMword Spsr[7]; /* the exception psr's */
armemu.c 2478 case 0x14: /* CMP reg and MRS SPSR and SWP byte. */
2571 /* MRS SPSR */
2624 case 0x16: /* CMN reg and MSR reg to SPSR */
3186 case 0x36: /* CMN immed and MSR immed to SPSR */
5063 state->Cpsr = state->Spsr[state->Bank];

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