HomeSort by: relevance | last modified time | path
    Searched refs:Src0RC (Results 1 - 4 of 4) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
SIFixSGPRCopies.cpp 684 const TargetRegisterClass *DstRC, *Src0RC, *Src1RC;
686 Src0RC = MRI->getRegClass(MI.getOperand(1).getReg());
689 (TRI->hasVectorRegisters(Src0RC) ||
SIInstrInfo.cpp 5481 const TargetRegisterClass *Src0RC = MRI.getRegClass(Src0);
5482 if (DstRC != Src0RC) {
6336 const TargetRegisterClass *Src0RC = Src0.isReg() ?
6340 const TargetRegisterClass *Src0SubRC = RI.getSubRegClass(Src0RC, AMDGPU::sub0);
6342 MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
6352 MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
6402 const TargetRegisterClass *Src0RC = MRI.getRegClass(Src0.getReg());
6404 const TargetRegisterClass *Src0SubRC = RI.getSubRegClass(Src0RC, AMDGPU::sub0);
6407 MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
6413 MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
    [all...]
AMDGPUInstructionSelector.cpp 732 const TargetRegisterClass *Src0RC =
739 Src0RC = TRI.getSubClassWithSubReg(Src0RC, SubReg);
740 if (!Src0RC || !Src1RC)
744 !RBI.constrainGenericRegister(Src0Reg, *Src0RC, *MRI) ||
SIISelLowering.cpp 3965 const TargetRegisterClass *Src0RC = Src0.isReg()
3973 TRI->getSubRegClass(Src0RC, AMDGPU::sub0);
3978 MI, MRI, Src0, Src0RC, AMDGPU::sub0, Src0SubRC);
3983 MI, MRI, Src0, Src0RC, AMDGPU::sub1, Src0SubRC);

Completed in 32 milliseconds