| /src/external/apache2/llvm/dist/llvm/lib/ExecutionEngine/Interpreter/ |
| Execution.cpp | 105 Dest.TY##Val = Src1.TY##Val OP Src2.TY##Val; \
108 static void executeFAddInst(GenericValue &Dest, GenericValue Src1,
119 static void executeFSubInst(GenericValue &Dest, GenericValue Src1,
130 static void executeFMulInst(GenericValue &Dest, GenericValue Src1,
141 static void executeFDivInst(GenericValue &Dest, GenericValue Src1,
152 static void executeFRemInst(GenericValue &Dest, GenericValue Src1,
156 Dest.FloatVal = fmod(Src1.FloatVal, Src2.FloatVal);
159 Dest.DoubleVal = fmod(Src1.DoubleVal, Src2.DoubleVal);
169 Dest.IntVal = APInt(1,Src1.IntVal.OP(Src2.IntVal)); \
175 assert(Src1.AggregateVal.size() == Src2.AggregateVal.size());
[all...] |
| /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/GlobalISel/ |
| MachineIRBuilder.h | 993 /// Build and insert \p Res = G_SHUFFLE_VECTOR \p Src1, \p Src2, \p Mask
998 MachineInstrBuilder buildShuffleVector(const DstOp &Res, const SrcOp &Src1,
1397 const SrcOp &Src1,
1399 return buildInstr(TargetOpcode::G_ADD, {Dst}, {Src0, Src1}, Flags);
1414 const SrcOp &Src1,
1416 return buildInstr(TargetOpcode::G_SUB, {Dst}, {Src0, Src1}, Flags);
1430 const SrcOp &Src1,
1432 return buildInstr(TargetOpcode::G_MUL, {Dst}, {Src0, Src1}, Flags);
1436 const SrcOp &Src1,
1438 return buildInstr(TargetOpcode::G_UMULH, {Dst}, {Src0, Src1}, Flags)
[all...] |
| GISelKnownBits.h | 38 void computeKnownBitsMin(Register Src0, Register Src1, KnownBits &Known,
42 unsigned computeNumSignBitsMin(Register Src0, Register Src1,
|
| MIPatternMatch.h | 521 Src1Ty Src1;
524 TernaryOp_match(const Src0Ty &Src0, const Src1Ty &Src1, const Src2Ty &Src2)
525 : Src0(Src0), Src1(Src1), Src2(Src2) {}
532 Src1.match(MRI, TmpMI->getOperand(2).getReg()) &&
542 m_GInsertVecElt(const Src0Ty &Src0, const Src1Ty &Src1, const Src2Ty &Src2) {
544 TargetOpcode::G_INSERT_VECTOR_ELT>(Src0, Src1, Src2);
549 m_GISelect(const Src0Ty &Src0, const Src1Ty &Src1, const Src2Ty &Src2) {
551 Src0, Src1, Src2);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| R600ExpandSpecialInstrs.cpp | 112 R600::ZERO); // src1
149 Register Src1 =
150 BMI->getOperand(TII->getOperandIdx(Opcode, R600::OpName::src1))
153 (void) Src1;
155 (TRI.getEncodingValue(Src1) & 0xff) < 127)
156 assert(TRI.getHWRegChan(Src0) == TRI.getHWRegChan(Src1));
200 unsigned Src1 = 0;
204 int Src1Idx = TII->getOperandIdx(MI, R600::OpName::src1);
206 Src1 = MI.getOperand(Src1Idx).getReg();
212 Src1 = TRI.getSubReg(Src1, SubRegIndex)
[all...] |
| AMDGPUInstCombineIntrinsic.cpp | 43 static APFloat fmed3AMDGCN(const APFloat &Src0, const APFloat &Src1,
45 APFloat Max3 = maxnum(maxnum(Src0, Src1), Src2);
50 return maxnum(Src1, Src2);
52 APFloat::cmpResult Cmp1 = Max3.compare(Src1);
57 return maxnum(Src0, Src1);
279 Value *Src1 = II.getArgOperand(1);
280 const ConstantInt *CMask = dyn_cast<ConstantInt>(Src1);
286 if (isa<UndefValue>(Src1)) {
324 II, 1, ConstantInt::get(Src1->getType(), Mask & ~(S_NAN | Q_NAN)));
337 {Src0, ConstantInt::get(Src1->getType(), Mask & FullMask)})
[all...] |
| SIOptimizeExecMasking.cpp | 105 const MachineOperand &Src1 = MI.getOperand(1);
106 if (Src1.isReg() && Src1.getReg() == AMDGPU::EXEC)
121 const MachineOperand &Src1 = MI.getOperand(1);
122 if (Src1.isReg() && Src1.getReg() == AMDGPU::EXEC_LO)
429 MachineOperand &Src1 = SaveExecInst->getOperand(2);
434 OtherOp = &Src1;
435 } else if (Src1.isReg() && Src1.getReg() == CopyFromExec)
[all...] |
| GCNDPPCombine.cpp | 15 // $res = VALU $dpp_value [, src1]
19 // $res = VALU_DPP $combined_old, $vgpr_to_be_read_from_other_lane, [src1,]
32 // -> $combined_old = src1,
261 if (auto *Src1 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src1)) {
262 if (!TII->isOperandLegal(*DPPInst.getInstr(), NumOperands, Src1)) {
263 LLVM_DEBUG(dbgs() << " failed: src1 is illegal\n");
267 DPPInst.add(*Src1);
352 auto *Src1 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src1);
[all...] |
| SIPeepholeSDWA.cpp | 312 } else if (TII->getNamedOperand(*MI, AMDGPU::OpName::src1) == SrcOp) {
349 // If this is not src0 then it could be src1
350 Src = TII->getNamedOperand(MI, AMDGPU::OpName::src1);
545 MachineOperand *Src1 = TII->getNamedOperand(MI, AMDGPU::OpName::src1);
547 if (Src1->getReg().isPhysical() || Dst->getReg().isPhysical())
553 Dst, Src1, *Imm == 16 ? WORD_1 : BYTE_3, UNUSED_PAD);
556 Src1, Dst, *Imm == 16 ? WORD_1 : BYTE_3, false, false,
582 MachineOperand *Src1 = TII->getNamedOperand(MI, AMDGPU::OpName::src1);
[all...] |
| SIShrinkInstructions.cpp | 182 const MachineOperand &Src1 = MI.getOperand(1);
183 if (!Src1.isImm())
194 if (isKImmOrKUImmOperand(TII, Src1, HasUImm)) {
208 if ((TII->sopkIsZext(SOPKOpc) && isKUImmOperand(TII, Src1)) ||
209 (!TII->sopkIsZext(SOPKOpc) && isKImmOperand(TII, Src1))) {
316 MachineOperand *Src1 = &MI.getOperand(2);
318 MachineOperand *SrcImm = Src1;
651 MachineOperand *Src1 = &MI.getOperand(2);
653 if (!Src0->isReg() && Src1->isReg()) {
655 std::swap(Src0, Src1);
[all...] |
| SIInstrInfo.cpp | 2022 MachineOperand &Src1,
2030 "All commutable instructions have both src0 and src1 modifiers");
2081 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1) ==
2086 MachineOperand &Src1 = MI.getOperand(Src1Idx);
2089 if (Src0.isReg() && Src1.isReg()) {
2096 } else if (Src0.isReg() && !Src1.isReg()) {
2099 CommutedMI = swapRegAndNonRegOperand(MI, Src0, Src1);
2100 } else if (!Src0.isReg() && Src1.isReg()) {
2102 CommutedMI = swapRegAndNonRegOperand(MI, Src1, Src0);
2110 Src1, AMDGPU::OpName::src1_modifiers)
[all...] |
| SIFoldOperands.cpp | 221 else if (OpNo == AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src1))
866 UseMI->RemoveOperand(2); // Remove exec read (or src1 for readlane)
885 UseMI->RemoveOperand(2); // Remove exec read (or src1 for readlane)
1066 int Src1Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1);
1069 MachineOperand *Src1 = getImmOrMaterializedImm(MRI, MI->getOperand(Src1Idx));
1071 if (!Src0->isImm() && !Src1->isImm())
1077 if (Src0->isImm() && Src1->isImm()) {
1079 if (!evalBinaryInstruction(Opc, NewImm, Src0->getImm(), Src1->getImm()))
1096 if (Src0->isImm() && !Src1->isImm()) {
1097 std::swap(Src0, Src1);
[all...] |
| SIFixSGPRCopies.cpp | 719 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::src1);
721 MachineOperand &Src1 = MI.getOperand(Src1Idx);
726 (Src1.isReg() && TRI->isSGPRReg(*MRI, Src1.getReg()) &&
727 Src1.getReg() != AMDGPU::M0)) {
734 for (MachineOperand *MO : {&Src0, &Src1}) {
756 // Move src1 to be in M0
759 .add(Src1);
760 Src1.ChangeToRegister(AMDGPU::M0, false);
|
| SILoadStoreOptimizer.cpp | 1462 const auto *Src1 = TII->getNamedOperand(*Paired.I, AMDGPU::OpName::vdata);
1467 .add(*Src1)
1617 const auto *Src1 = TII->getNamedOperand(*Paired.I, AMDGPU::OpName::vdata);
1622 .add(*Src1)
1791 const auto *Src1 = TII->getNamedOperand(*BaseLoDef, AMDGPU::OpName::src1);
1795 BaseLo = *Src1;
1797 if (!(Offset0P = extractConstOffset(*Src1)))
1803 Src1 = TII->getNamedOperand(*BaseHiDef, AMDGPU::OpName::src1);
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/ |
| SystemZSelectionDAGInfo.cpp | 144 // Use CLC to compare [Src1, Src1 + Size) with [Src2, Src2 + Size),
147 SDValue Src1, SDValue Src2, uint64_t Size) {
149 EVT PtrVT = Src1.getValueType();
159 return DAG.getNode(SystemZISD::CLC_LOOP, DL, VTs, Chain, Src1, Src2,
162 return DAG.getNode(SystemZISD::CLC, DL, VTs, Chain, Src1, Src2,
181 SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, SDValue Src1,
188 SDValue CCReg = emitCLC(DAG, DL, Chain, Src2, Src1, Bytes);
232 SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, SDValue Src1,
235 SDVTList VTs = DAG.getVTList(Src1.getValueType(), MVT::i32, MVT::Other)
[all...] |
| SystemZSelectionDAGInfo.h | 41 SDValue Src1, SDValue Src2, SDValue Size,
57 SDValue Src1, SDValue Src2,
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| AArch64AdvSIMDScalarPass.cpp | 299 unsigned Src1 = 0, SubReg1;
328 Src1 = MOSrc1->getReg();
347 if (!Src1) {
349 Src1 = MRI->createVirtualRegister(&AArch64::FPR64RegClass);
350 insertCopy(TII, MI, Src1, OrigSrc1, KillSrc1);
364 .addReg(Src1, getKillRegState(KillSrc1), SubReg1);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| HexagonGenMux.cpp | 134 unsigned getMuxOpcode(const MachineOperand &Src1,
208 unsigned HexagonGenMux::getMuxOpcode(const MachineOperand &Src1,
210 bool IsReg1 = Src1.isReg(), IsReg2 = Src2.isReg();
305 MachineOperand *Src1 = &Def1.getOperand(2), *Src2 = &Def2.getOperand(2);
306 Register SR1 = Src1->isReg() ? Src1->getReg() : Register();
323 MachineOperand *SrcT = (MinX == CI.TrueX) ? Src1 : Src2;
324 MachineOperand *SrcF = (MinX == CI.FalseX) ? Src1 : Src2;
|
| HexagonPeephole.cpp | 155 MachineOperand &Src1 = MI.getOperand(1);
157 if (Src1.getImm() != 0)
172 MachineOperand &Src1 = MI.getOperand(1);
177 Register SrcReg = Src1.getReg();
|
| /src/sys/external/bsd/gnu-efi/dist/lib/ |
| dpath.c | 128 IN EFI_DEVICE_PATH *Src1,
131 // Src1 may have multiple "instances" and each instance is appended
132 // Src2 is appended to each instance is Src1. (E.g., it's possible
144 if (!Src1) {
150 ASSERT (!IsDevicePathUnpacked (Src1));
151 return DuplicateDevicePath (Src1);
158 // ASSERT (!IsDevicePathUnpacked (Src1));
162 // Append Src2 to every instance in Src1
165 Src1Size = DevicePathSize(Src1);
166 Src1Inst = DevicePathInstanceCount(Src1);
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Transforms/Scalar/ |
| InferAddressSpaces.cpp | 657 Constant *Src1 = CE->getOperand(2);
659 Src1->getType()->getPointerAddressSpace()) {
663 ConstantExpr::getAddrSpaceCast(Src1, TargetType));
843 Value *Src1 = Op.getOperand(2);
849 auto J = InferredAddrSpace.find(Src1);
851 J->second : Src1->getType()->getPointerAddressSpace();
854 auto *C1 = dyn_cast<Constant>(Src1);
|
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/ |
| GISelKnownBits.cpp | 97 /// Compute known bits for the intersection of \p Src0 and \p Src1
98 void GISelKnownBits::computeKnownBitsMin(Register Src0, Register Src1,
102 // Test src1 first, since we canonicalize simpler expressions to the RHS.
103 computeKnownBitsImpl(Src1, Known, DemandedElts, Depth);
507 /// Compute number of sign bits for the intersection of \p Src0 and \p Src1
508 unsigned GISelKnownBits::computeNumSignBitsMin(Register Src0, Register Src1,
511 // Test src1 first, since we canonicalize simpler expressions to the RHS.
512 unsigned Src1SignBits = computeNumSignBits(Src1, DemandedElts, Depth);
|
| CSEMIRBuilder.cpp | 200 const SrcOp &Src1 = SrcOps[1];
202 ConstantFoldExtOp(Opc, Src0.getReg(), Src1.getImm(), *getMRI()))
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/ |
| AArch64PostLegalizerCombiner.cpp | 53 Register Src1 = MI.getOperand(1).getReg();
63 auto *FAddMI = getOpcodeDef(TargetOpcode::G_FADD, Src1, MRI);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/ |
| RISCVISelDAGToDAG.cpp | 441 SDValue Src1 = Node->getOperand(1);
453 MVT Src1VT = Src1.getSimpleValueType();
502 CurDAG->getMachineNode(VMSLTOpcode, DL, VT, {Src1, Src2, VL, SEW}),
510 SDValue Src1 = Node->getOperand(2);
522 MVT Src1VT = Src1.getSimpleValueType();
595 CurDAG->getMachineNode(VMSLTOpcode, DL, VT, {Src1, Src2, VL, SEW}),
606 {MaskedOff, Src1, Src2, Mask, VL, SEW}),
|
