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    Searched refs:Src1Reg (Results 1 - 16 of 16) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/
SystemZPostRewrite.cpp 111 Register Src1Reg = MBBI->getOperand(1).getReg();
114 bool Src1IsHigh = SystemZ::isHighReg(Src1Reg);
120 if (DestReg != Src1Reg && DestReg != Src2Reg) {
126 Src1Reg = DestReg;
139 if (DestReg != Src1Reg && DestReg == Src2Reg) {
141 std::swap(Src1Reg, Src2Reg);
  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/MCTargetDesc/
HexagonMCCompound.cpp 81 unsigned DstReg, SrcReg, Src1Reg, Src2Reg;
98 Src1Reg = MI.getOperand(1).getReg();
101 HexagonMCInstrInfo::isIntRegForSubInst(Src1Reg) &&
143 Src1Reg = MI.getOperand(1).getReg();
145 HexagonMCInstrInfo::isIntRegForSubInst(Src1Reg) &&
157 Src1Reg = MI.getOperand(0).getReg();
158 if (Hexagon::P0 == Src1Reg || Hexagon::P1 == Src1Reg)
HexagonMCDuplexInfo.cpp 190 unsigned DstReg, PredReg, SrcReg, Src1Reg, Src2Reg;
322 Src1Reg = MCI.getOperand(0).getReg();
324 if (HexagonMCInstrInfo::isIntReg(Src1Reg) &&
326 Hexagon::R29 == Src1Reg && inRange<5, 2>(MCI, 1)) {
330 if (HexagonMCInstrInfo::isIntRegForSubInst(Src1Reg) &&
338 Src1Reg = MCI.getOperand(0).getReg();
340 if (HexagonMCInstrInfo::isIntRegForSubInst(Src1Reg) &&
357 Src1Reg = MCI.getOperand(0).getReg();
359 if (HexagonMCInstrInfo::isIntRegForSubInst(Src1Reg) &&
367 Src1Reg = MCI.getOperand(0).getReg()
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
HexagonInstrInfo.cpp 1201 Register Src1Reg = MI.getOperand(1).getReg();
1203 Register Src1SubHi = HRI.getSubReg(Src1Reg, Hexagon::isub_hi);
1204 Register Src1SubLo = HRI.getSubReg(Src1Reg, Hexagon::isub_lo);
1225 Register Src1Reg = MI.getOperand(1).getReg();
1228 Register Src1SubHi = HRI.getSubReg(Src1Reg, Hexagon::isub_hi);
1229 Register Src1SubLo = HRI.getSubReg(Src1Reg, Hexagon::isub_lo);
3328 unsigned DstReg, SrcReg, Src1Reg, Src2Reg;
3343 Src1Reg = MI.getOperand(1).getReg();
3347 isIntRegForSubInst(Src1Reg) && isIntRegForSubInst(Src2Reg))
3380 Src1Reg = MI.getOperand(1).getReg()
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/
AArch64PostLegalizerLowering.cpp 647 Register Src1Reg = MI.getOperand(1).getReg();
648 const LLT SrcTy = MRI.getType(Src1Reg);
699 Register Src1Reg = MI.getOperand(1).getReg();
700 const LLT SrcTy = MRI.getType(Src1Reg);
713 {Src1Reg, Undef.getReg(0)})
AArch64InstructionSelector.cpp 1668 Register Src1Reg = I.getOperand(1).getReg();
1698 auto Shl = MIB.buildInstr(Opc, {DstReg}, {Src1Reg});
1714 Register Src1Reg = I.getOperand(1).getReg();
1761 auto SShl = MIB.buildInstr(Opc, {DstReg}, {Src1Reg, Neg});
3672 Register Src1Reg = I.getOperand(1).getReg();
3676 emitLaneInsert(None, Tmp.getReg(0), Src1Reg, /* LaneIdx */ 0, RB, MIB);
4569 Register Src1Reg = I.getOperand(1).getReg();
4570 const LLT Src1Ty = MRI.getType(Src1Reg);
4611 MachineInstr *Concat = emitVectorConcat(None, Src1Reg, Src2Reg, MIB);
4637 {&AArch64::QQRegClass}, {Src1Reg})
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
MLxExpansionPass.cpp 275 Register Src1Reg = MI->getOperand(2).getReg();
291 .addReg(Src1Reg, getKillRegState(Src1Kill))
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
R600InstrInfo.h 271 unsigned Src1Reg = 0) const;
R600InstrInfo.cpp 1220 unsigned Src1Reg) const {
1224 if (Src1Reg) {
1238 if (Src1Reg) {
1239 MIB.addReg(Src1Reg) // $src1
AMDGPUInstructionSelector.cpp 424 Register Src1Reg = I.getOperand(3).getReg();
445 !RBI.constrainGenericRegister(Src1Reg, AMDGPU::SReg_32RegClass, *MRI))
704 Register Src1Reg = I.getOperand(2).getReg();
705 LLT Src1Ty = MRI->getType(Src1Reg);
731 const RegisterBank *Src1Bank = RBI.getRegBank(Src1Reg, *MRI, TRI);
745 !RBI.constrainGenericRegister(Src1Reg, *Src1RC, *MRI))
751 .addReg(Src1Reg)
916 Register Src1Reg = I.getOperand(3).getReg();
920 for (Register Reg : { DstReg, Src0Reg, Src1Reg })
2796 Register Src1Reg = MI.getOperand(2).getReg()
    [all...]
AMDGPULegalizerInfo.cpp 1945 Register Src1Reg = MI.getOperand(2).getReg();
1949 auto Div = B.buildFDiv(Ty, Src0Reg, Src1Reg, Flags);
1952 B.buildFMA(DstReg, Neg, Src1Reg, Src0Reg, Flags);
AMDGPURegisterBankInfo.cpp 4011 Register Src1Reg = MI.getOperand(3).getReg();
4013 unsigned Src1Size = MRI.getType(Src1Reg).getSizeInBits();
SIInstrInfo.cpp 2813 Register Src1Reg = Src1->getReg();
2815 Src0->setReg(Src1Reg);
  /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
MipsFastISel.cpp 1044 unsigned Src1Reg = getRegForValue(SI->getTrueValue());
1048 if (!Src1Reg || !Src2Reg || !CondReg)
1066 .addReg(Src1Reg).addReg(ZExtCondReg).addReg(TempReg);
1939 unsigned Src1Reg = getRegForValue(I->getOperand(1));
1940 if (!Src0Reg || !Src1Reg)
1943 emitInst(DivOpc).addReg(Src0Reg).addReg(Src1Reg);
1944 emitInst(Mips::TEQ).addReg(Src1Reg).addReg(Mips::ZERO).addImm(7);
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64FastISel.cpp 2633 unsigned Src1Reg = getRegForValue(Src1Val);
2634 if (!Src1Reg)
2642 Src1Reg = emitLogicalOp_ri(ISD::XOR, MVT::i32, Src1Reg, 1);
2644 unsigned ResultReg = fastEmitInst_rr(Opc, &AArch64::GPR32RegClass, Src1Reg,
2756 unsigned Src1Reg = getRegForValue(SI->getTrueValue());
2759 if (!Src1Reg || !Src2Reg)
2763 Src2Reg = fastEmitInst_rri(Opc, RC, Src1Reg, Src2Reg, ExtraCC);
2765 unsigned ResultReg = fastEmitInst_rri(Opc, RC, Src1Reg, Src2Reg, CC);
4545 unsigned Src1Reg = getRegForValue(I->getOperand(1))
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/
LegalizerHelper.cpp 6289 Register Src1Reg = MI.getOperand(2).getReg();
6306 Val = Mask[0] == 0 ? Src0Reg : Src1Reg;
6325 BuildVec.push_back(Idx == 0 ? Src0Reg : Src1Reg);
6328 Register SrcVec = Idx < NumElts ? Src0Reg : Src1Reg;

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