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    Searched refs:SrcR (Results 1 - 7 of 7) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
RDFCopy.cpp 47 RegisterRef SrcR = DFG.makeRegRef(Src.getReg(), Src.getSubReg());
49 assert(Register::isPhysicalRegister(SrcR.Reg));
52 TRI.getMinimalPhysRegClass(SrcR.Reg))
54 EM.insert(std::make_pair(DstR, SrcR));
HexagonGenInsert.cpp 466 // ... = insert(SrcR, InsR, #Wdh, #Off)
469 : SrcR(SR), InsR(IR), Wdh(W), Off(O) {}
471 unsigned SrcR, InsR;
487 unsigned SrcR = P.IFR.SrcR, InsR = P.IFR.InsR;
488 OS << '(' << printReg(SrcR, P.TRI) << ',' << printReg(InsR, P.TRI)
534 bool isValidInsertForm(unsigned DstR, unsigned SrcR, unsigned InsR,
684 bool HexagonGenInsert::isValidInsertForm(unsigned DstR, unsigned SrcR,
687 const TargetRegisterClass *SrcRC = MRI->getRegClass(SrcR);
881 unsigned SrcR = *I
    [all...]
HexagonRDFOpt.cpp 113 auto mapRegs = [&EM] (RegisterRef DstR, RegisterRef SrcR) -> void {
114 EM.insert(std::make_pair(DstR, SrcR));
HexagonFrameLowering.cpp 1757 Register SrcR = MI->getOperand(1).getReg();
1759 !Hexagon::ModRegsRegClass.contains(SrcR))
1781 Register SrcR = MI->getOperand(2).getReg();
1785 // TmpR = C2_tfrpr SrcR if SrcR is a predicate register
1786 // TmpR = A2_tfrcrr SrcR if SrcR is a modifier register
1791 .addReg(SrcR, getKillRegState(IsKill));
1844 Register SrcR = MI->getOperand(2).getReg();
1860 .addReg(SrcR, getKillRegState(IsKill)
    [all...]
HexagonBitSimplify.cpp 2220 unsigned SrcR = B0.RefI.Reg;
2229 if (V.RefI.Reg != SrcR || V.RefI.Pos != Pos+i)
2246 // The Z lower bits should now match SrcR.
2248 if (S0.Type != BitTracker::BitValue::Ref || S0.RefI.Reg != SrcR)
2265 if (V.RefI.Reg != SrcR || V.RefI.Pos != P+I)
2280 if (MRI.getRegClass(SrcR)->getID() == Hexagon::DoubleRegsRegClassID)
2282 if (!validateReg({SrcR,SrcSR}, Hexagon::A4_bitspliti, 1))
2292 if (Op1.getReg() != SrcR || Op1.getSubReg() != SrcSR)
2311 .addReg(SrcR, 0, SrcSR)
HexagonConstPropagation.cpp 1949 RegisterSubReg SrcR(MI.getOperand(1));
1950 bool Eval = evaluateCOPY(SrcR, Inputs, RC);
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86FixupLEAs.cpp 536 const MachineOperand &SrcR = SrcR1 == DstR ? Base : Index;
538 .add(SrcR)

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