| /src/external/apache2/llvm/dist/llvm/lib/Target/NVPTX/ |
| NVPTXInstrInfo.cpp | 38 const TargetRegisterClass *SrcRC = MRI.getRegClass(SrcReg);
40 if (RegInfo.getRegSizeInBits(*DestRC) != RegInfo.getRegSizeInBits(*SrcRC))
49 Op = (SrcRC == &NVPTX::Int32RegsRegClass ? NVPTX::IMOV32rr
52 Op = (SrcRC == &NVPTX::Int64RegsRegClass ? NVPTX::IMOV64rr
55 Op = (SrcRC == &NVPTX::Float16RegsRegClass ? NVPTX::FMOV16rr
60 Op = (SrcRC == &NVPTX::Float32RegsRegClass ? NVPTX::FMOV32rr
63 Op = (SrcRC == &NVPTX::Float64RegsRegClass ? NVPTX::FMOV64rr
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AVR/ |
| AVRRegisterInfo.h | 55 const TargetRegisterClass *SrcRC,
|
| AVRRegisterInfo.cpp | 280 const TargetRegisterClass *SrcRC,
290 return TargetRegisterInfo::shouldCoalesce(MI, SrcRC, SubReg, DstRC, DstSubReg, NewRC, LIS);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| SIFixSGPRCopies.cpp | 147 const TargetRegisterClass *SrcRC = SrcReg.isVirtual()
152 // SrcRC = TRI.getSubRegClass(SrcRC, Copy.getOperand(1).getSubReg());
158 return std::make_pair(SrcRC, DstRC);
161 static bool isVGPRToSGPRCopy(const TargetRegisterClass *SrcRC,
164 return SrcRC != &AMDGPU::VReg_1RegClass && TRI.isSGPRClass(DstRC) &&
165 TRI.hasVectorRegisters(SrcRC);
168 static bool isSGPRToVGPRCopy(const TargetRegisterClass *SrcRC,
171 return DstRC != &AMDGPU::VReg_1RegClass && TRI.isSGPRClass(SrcRC) &&
237 const TargetRegisterClass *SrcRC, *DstRC
[all...] |
| AMDGPUInstructionSelector.cpp | 106 const TargetRegisterClass *SrcRC
108 if (!DstRC || DstRC != SrcRC)
112 RBI.constrainGenericRegister(Src.getReg(), *SrcRC, *MRI);
139 const TargetRegisterClass *SrcRC
150 Register MaskedReg = MRI->createVirtualRegister(SrcRC);
157 TRI.isSGPRClass(SrcRC) ? AMDGPU::S_AND_B32 : AMDGPU::V_AND_B32_e32;
167 MRI->setRegClass(SrcReg, SrcRC);
483 const TargetRegisterClass *SrcRC =
485 if (!SrcRC)
489 SrcRC = TRI.getSubClassWithSubReg(SrcRC, SubReg)
[all...] |
| SIRegisterInfo.h | 210 const TargetRegisterClass *SrcRC,
245 const TargetRegisterClass *SrcRC,
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| HexagonRegisterInfo.h | 59 bool shouldCoalesce(MachineInstr *MI, const TargetRegisterClass *SrcRC,
|
| HexagonRegisterInfo.cpp | 348 const TargetRegisterClass *SrcRC, unsigned SubReg,
359 bool SmallSrc = SrcRC->getID() == Hexagon::HvxVRRegClass.getID();
|
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| TargetRegisterInfo.cpp | 384 const TargetRegisterClass *SrcRC,
387 if (DefRC == SrcRC)
393 return TRI.getCommonSuperRegClass(SrcRC, SrcSubReg, DefRC, DefSubReg,
401 std::swap(DefRC, SrcRC);
406 return TRI.getMatchingSuperRegClass(SrcRC, DefRC, SrcSubReg) != nullptr;
409 return TRI.getCommonSubClass(DefRC, SrcRC) != nullptr;
414 const TargetRegisterClass *SrcRC,
417 return shareSameRegisterFile(*this, DefRC, DefSubReg, SrcRC, SrcSubReg);
|
| DetectDeadLanes.cpp | 155 const TargetRegisterClass *SrcRC = MRI.getRegClass(SrcReg);
156 if (DstRC == SrcRC)
181 return !TRI.getCommonSuperRegClass(SrcRC, SrcSubIdx, DstRC, DstSubIdx, PreA,
184 return !TRI.getMatchingSuperRegClass(SrcRC, DstRC, SrcSubIdx);
186 return !TRI.getMatchingSuperRegClass(DstRC, SrcRC, DstSubIdx);
187 return !TRI.getCommonSubClass(SrcRC, DstRC);
|
| RegisterCoalescer.cpp | 478 const TargetRegisterClass *SrcRC = MRI.getRegClass(Src);
487 NewRC = TRI.getCommonSuperRegClass(SrcRC, SrcSub, DstRC, DstSub,
494 NewRC = TRI.getMatchingSuperRegClass(DstRC, SrcRC, DstSub);
498 NewRC = TRI.getMatchingSuperRegClass(SrcRC, DstRC, SrcSub);
501 NewRC = TRI.getCommonSubClass(DstRC, SrcRC);
516 CrossClass = NewRC != DstRC || NewRC != SrcRC;
1881 auto SrcRC = MRI->getRegClass(CP.getSrcReg());
1887 std::swap(SrcRC, DstRC);
1889 if (!TRI->shouldCoalesce(CopyMI, SrcRC, SrcIdx, DstRC, DstIdx,
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| PPCVSXCopy.cpp | 99 const TargetRegisterClass *SrcRC = &PPC::VSLRCRegClass;
105 Register NewVReg = MRI.createVirtualRegister(SrcRC);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| X86RegisterInfo.h | 75 const TargetRegisterClass *SrcRC,
|
| X86InstructionSelector.cpp | 112 const TargetRegisterClass *SrcRC) const;
248 const TargetRegisterClass *SrcRC =
252 if (SrcRC != DstRC) {
260 .addImm(getSubRegIndex(SrcRC));
286 const TargetRegisterClass *SrcRC = getRegClassFromGRPhysReg(SrcReg);
288 if (DstRC != SrcRC) {
683 // SrcRC lives on a 128-bit vector class.
685 const TargetRegisterClass *SrcRC) {
688 (SrcRC == &X86::VR128RegClass || SrcRC == &X86::VR128XRegClass)
[all...] |
| X86DomainReassignment.cpp | 65 /// Return a register class equivalent to \p SrcRC, in \p Domain.
66 static const TargetRegisterClass *getDstRC(const TargetRegisterClass *SrcRC,
69 if (X86::GR8RegClass.hasSubClassEq(SrcRC))
71 if (X86::GR16RegClass.hasSubClassEq(SrcRC))
73 if (X86::GR32RegClass.hasSubClassEq(SrcRC))
75 if (X86::GR64RegClass.hasSubClassEq(SrcRC))
|
| X86RegisterInfo.cpp | 217 const TargetRegisterClass *SrcRC,
223 SrcRC->hasSuperClassEq(&X86::GR64RegClass) && SrcSubReg == X86::sub_32bit)
227 SrcRC, SrcSubReg);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/ |
| SystemZRegisterInfo.h | 156 /// SrcRC and DstRC will be morphed into NewRC if this returns true.
158 const TargetRegisterClass *SrcRC,
|
| SystemZRegisterInfo.cpp | 377 const TargetRegisterClass *SrcRC,
387 (getRegSizeInBits(*SrcRC) <= 64 || getRegSizeInBits(*DstRC) <= 64)))
394 unsigned WideOpNo = (getRegSizeInBits(*SrcRC) == 128 ? 1 : 0);
|
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/ |
| InstructionSelect.cpp | 225 auto SrcRC = MRI.getRegClass(SrcReg);
227 if (SrcRC == DstRC) {
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| ARMBaseRegisterInfo.h | 204 /// SrcRC and DstRC will be morphed into NewRC if this returns true
206 const TargetRegisterClass *SrcRC,
215 const TargetRegisterClass *SrcRC,
|
| ARMBaseRegisterInfo.cpp | 855 const TargetRegisterClass *SrcRC,
870 getRegSizeInBits(*SrcRC) < 256)
876 MRI.getTargetRegisterInfo()->getRegClassWeight(SrcRC);
915 const TargetRegisterClass *SrcRC,
919 SrcRC == &ARM::DPRRegClass &&
924 SrcRC, SrcSubReg);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| AArch64RegisterInfo.h | 132 /// SrcRC and DstRC will be morphed into NewRC if this returns true
133 bool shouldCoalesce(MachineInstr *MI, const TargetRegisterClass *SrcRC,
|
| /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| TargetRegisterInfo.h | 590 // subreg index DefSubReg, reading from another source with class SrcRC and
595 const TargetRegisterClass *SrcRC,
1022 /// SrcRC and DstRC will be morphed into NewRC if this returns true.
1024 const TargetRegisterClass *SrcRC,
|
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| ScheduleDAGFast.cpp | 382 const TargetRegisterClass *SrcRC,
385 CopyFromSU->CopySrcRC = SrcRC;
390 CopyToSU->CopyDstRC = SrcRC;
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/ |
| AArch64InstructionSelector.cpp | 864 const TargetRegisterClass *SrcRC;
866 std::tie(SrcRC, DstRC) = getRegClassesForCopy(I, TII, MRI, TRI, RBI);
902 if (!SrcRC) {
907 unsigned SrcSize = TRI.getRegSizeInBits(*SrcRC);
933 getSubRegForClass(SrcRC, TRI, SubReg);
2834 const TargetRegisterClass *SrcRC =
2836 if (!SrcRC)
2839 if (!RBI.constrainGenericRegister(SrcReg, *SrcRC, MRI) ||
2845 if (DstRC == SrcRC) {
2852 SrcRC == &AArch64::GPR64RegClass)
[all...] |
