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  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
PHIEliminationUtils.h 16 /// SrcReg when following the CFG edge to SuccMBB. This needs to be after
17 /// any def of SrcReg, but before any subsequent point where control flow
21 unsigned SrcReg);
RegisterCoalescer.h 36 Register SrcReg;
41 /// The sub-register index of the old SrcReg in the new coalesced register.
50 /// True when DstReg and SrcReg are reversed from the original
56 /// SrcReg and DstReg.
66 : TRI(tri), DstReg(PhysReg), SrcReg(VirtReg) {}
72 /// Swap SrcReg and DstReg. Return false if swapping is impossible
100 Register getSrcReg() const { return SrcReg; }
105 /// Return the subregister index that SrcReg will be coalesced into, or 0.
PHIEliminationUtils.cpp 16 // findCopyInsertPoint - Find a safe place in MBB to insert a copy from SrcReg
18 // SrcReg, but before any subsequent point where control flow might jump out of
22 unsigned SrcReg) {
41 for (MachineInstr &RI : MRI.def_instructions(SrcReg))
OptimizePHIs.cpp 113 Register SrcReg = MI->getOperand(i).getReg();
114 if (SrcReg == DstReg)
116 MachineInstr *SrcMI = MRI->getVRegDef(SrcReg);
122 SrcReg = SrcMI->getOperand(1).getReg();
123 SrcMI = MRI->getVRegDef(SrcReg);
133 if (SingleValReg != 0 && SingleValReg != SrcReg)
135 SingleValReg = SrcReg;
PHIElimination.cpp 427 Register SrcReg = MPhi->getOperand(i * 2 + 1).getReg();
430 isImplicitlyDefined(SrcReg, *MRI);
431 assert(Register::isVirtualRegister(SrcReg) &&
444 MachineInstr *SrcRegDef = MRI->getVRegDef(SrcReg);
450 // removed) there should be no other uses of the SrcReg.
451 assert(MRI->use_empty(SrcReg) &&
460 findPHICopyInsertPoint(&opBlock, &MBB, SrcReg);
474 if (MachineInstr *DefMI = MRI->getVRegDef(SrcReg))
481 SrcReg, SrcSubReg, IncomingReg);
485 // We only need to update the LiveVariables kill of SrcReg if this was th
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  /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
PPCRegisterInfo.h 26 inline static unsigned getCRFromCRBit(unsigned SrcReg) {
28 if (SrcReg == PPC::CR0LT || SrcReg == PPC::CR0GT ||
29 SrcReg == PPC::CR0EQ || SrcReg == PPC::CR0UN)
31 else if (SrcReg == PPC::CR1LT || SrcReg == PPC::CR1GT ||
32 SrcReg == PPC::CR1EQ || SrcReg == PPC::CR1UN)
34 else if (SrcReg == PPC::CR2LT || SrcReg == PPC::CR2GT |
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PPCFastISel.cpp 151 unsigned SrcReg, unsigned Flag = 0,
155 TII.get(TargetOpcode::COPY), TmpReg).addReg(SrcReg, Flag, SubReg);
164 bool PPCEmitStore(MVT VT, unsigned SrcReg, Address &Addr);
168 bool PPCEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
179 unsigned SrcReg, bool IsSigned);
180 unsigned PPCMoveToFPReg(MVT VT, unsigned SrcReg, bool IsSigned);
619 // Emit a store instruction to store SrcReg at Addr.
620 bool PPCFastISel::PPCEmitStore(MVT VT, unsigned SrcReg, Address &Addr) {
621 assert(SrcReg && "Nothing to store!");
625 const TargetRegisterClass *RC = MRI.getRegClass(SrcReg);
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  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
HexagonPeephole.cpp 140 Register SrcReg = Src.getReg();
142 if (DstReg.isVirtual() && SrcReg.isVirtual()) {
146 PeepholeMap[DstReg] = SrcReg;
160 Register SrcReg = Src2.getReg();
161 PeepholeMap[DstReg] = SrcReg;
177 Register SrcReg = Src1.getReg();
179 std::make_pair(*&SrcReg, Hexagon::isub_hi);
188 Register SrcReg = Src.getReg();
190 if (DstReg.isVirtual() && SrcReg.isVirtual()) {
194 PeepholeMap[DstReg] = SrcReg;
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  /src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/
SystemZCopyPhysRegs.cpp 86 Register SrcReg = MI->getOperand(1).getReg();
89 (SrcReg == SystemZ::CC || SystemZ::AR32BitRegClass.contains(SrcReg))) {
91 if (SrcReg == SystemZ::CC)
94 BuildMI(MBB, MI, DL, TII->get(SystemZ::EAR), Tmp).addReg(SrcReg);
98 else if (SrcReg.isVirtual() &&
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
Thumb1InstrInfo.h 41 const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
45 Register SrcReg, bool isKill, int FrameIndex,
Thumb1InstrInfo.cpp 42 MCRegister SrcReg, bool KillSrc) const {
47 assert(ARM::GPRRegClass.contains(DestReg, SrcReg) &&
50 if (st.hasV6Ops() || ARM::hGPRRegClass.contains(SrcReg)
53 .addReg(SrcReg, getKillRegState(KillSrc))
63 .addReg(SrcReg, getKillRegState(KillSrc))
71 .addReg(SrcReg, getKillRegState(KillSrc));
80 Register SrcReg, bool isKill, int FI,
84 (Register::isPhysicalRegister(SrcReg) && isARMLowRegister(SrcReg))) &&
88 (Register::isPhysicalRegister(SrcReg) && isARMLowRegister(SrcReg)))
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  /src/external/apache2/llvm/dist/llvm/lib/Target/BPF/
BPFInstrInfo.cpp 34 MCRegister SrcReg, bool KillSrc) const {
35 if (BPF::GPRRegClass.contains(DestReg, SrcReg))
37 .addReg(SrcReg, getKillRegState(KillSrc));
38 else if (BPF::GPR32RegClass.contains(DestReg, SrcReg))
40 .addReg(SrcReg, getKillRegState(KillSrc));
47 Register SrcReg = MI->getOperand(1).getReg();
79 .addReg(ScratchReg, RegState::Define).addReg(SrcReg)
93 .addReg(ScratchReg, RegState::Define).addReg(SrcReg).addImm(Offset);
100 .addReg(ScratchReg, RegState::Define).addReg(SrcReg).addImm(Offset);
107 .addReg(ScratchReg, RegState::Define).addReg(SrcReg).addImm(Offset)
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BPFInstrInfo.h 33 const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
39 MachineBasicBlock::iterator MBBI, Register SrcReg,
BPFMISimplifyPatchable.cpp 60 MachineInstr &MI, Register &SrcReg, Register &DstReg,
63 Register &SrcReg, const GlobalValue *GVal,
160 MachineBasicBlock &MBB, MachineInstr &MI, Register &SrcReg,
186 .addReg(SrcReg, 0, BPF::sub_32);
190 // All uses of DstReg replaced by SrcReg
191 processDstReg(MRI, DstReg, SrcReg, GVal, true, IsAma);
195 Register &DstReg, Register &SrcReg, const GlobalValue *GVal,
202 I->setReg(SrcReg);
271 Register SrcReg = MI.getOperand(1).getReg();
273 MachineInstr *DefInst = MRI->getUniqueVRegDef(SrcReg);
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  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/GlobalISel/
LegalizationArtifactCombiner.h 58 Register SrcReg = lookThroughCopyInstrs(MI.getOperand(1).getReg());
62 if (mi_match(SrcReg, MRI, m_GTrunc(m_Reg(TruncSrc)))) {
66 markInstAndDefDead(MI, *MRI.getVRegDef(SrcReg), DeadInsts);
73 if (mi_match(SrcReg, MRI,
84 auto *SrcMI = MRI.getVRegDef(SrcReg);
107 Register SrcReg = lookThroughCopyInstrs(MI.getOperand(1).getReg());
113 if (mi_match(SrcReg, MRI, m_GTrunc(m_Reg(TruncSrc))) ||
114 mi_match(SrcReg, MRI, m_GSExt(m_Reg(SextSrc)))) {
120 LLT SrcTy = MRI.getType(SrcReg);
127 markInstAndDefDead(MI, *MRI.getVRegDef(SrcReg), DeadInsts)
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  /src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/
SparcInstrInfo.cpp 308 MCRegister SrcReg, bool KillSrc) const {
321 if (SP::IntRegsRegClass.contains(DestReg, SrcReg))
323 .addReg(SrcReg, getKillRegState(KillSrc));
324 else if (SP::IntPairRegClass.contains(DestReg, SrcReg)) {
329 } else if (SP::FPRegsRegClass.contains(DestReg, SrcReg))
331 .addReg(SrcReg, getKillRegState(KillSrc));
332 else if (SP::DFPRegsRegClass.contains(DestReg, SrcReg)) {
335 .addReg(SrcReg, getKillRegState(KillSrc));
342 } else if (SP::QFPRegsRegClass.contains(DestReg, SrcReg)) {
346 .addReg(SrcReg, getKillRegState(KillSrc))
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  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/
InstructionSelect.cpp 170 Register SrcReg = MI.getOperand(1).getReg();
178 MRI.setRegClass(SrcReg, DstRC);
179 assert(canReplaceReg(DstReg, SrcReg, MRI) &&
182 MRI.replaceRegWith(DstReg, SrcReg);
221 Register SrcReg = MI.getOperand(1).getReg();
223 if (Register::isVirtualRegister(SrcReg) &&
225 auto SrcRC = MRI.getRegClass(SrcReg);
228 MRI.replaceRegWith(DstReg, SrcReg);
  /src/external/apache2/llvm/dist/llvm/lib/Target/MSP430/
MSP430InstrInfo.h 39 const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
44 Register SrcReg, bool isKill,
  /src/external/apache2/llvm/dist/llvm/lib/Target/XCore/
XCoreInstrInfo.h 66 const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
71 Register SrcReg, bool isKill, int FrameIndex,
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
AMDGPUPostLegalizerCombiner.cpp 170 Register SrcReg = MI.getOperand(1).getReg();
171 unsigned SrcSize = MRI.getType(SrcReg).getSizeInBits();
174 return Helper.getKnownBits()->maskedValueIsZero(SrcReg, Mask);
186 Register SrcReg = MI.getOperand(1).getReg();
188 LLT SrcTy = MRI.getType(SrcReg);
190 SrcReg = B.buildAnyExtOrTrunc(S32, SrcReg).getReg(0);
194 {SrcReg}, MI.getFlags());
197 {SrcReg}, MI.getFlags());
206 Register SrcReg = MI.getOperand(1).getReg()
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  /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
MipsSEInstrInfo.cpp 86 MCRegister SrcReg, bool KillSrc) const {
91 if (Mips::GPR32RegClass.contains(SrcReg)) {
96 } else if (Mips::CCRRegClass.contains(SrcReg))
98 else if (Mips::FGR32RegClass.contains(SrcReg))
100 else if (Mips::HI32RegClass.contains(SrcReg)) {
102 SrcReg = 0;
103 } else if (Mips::LO32RegClass.contains(SrcReg)) {
105 SrcReg = 0;
106 } else if (Mips::HI32DSPRegClass.contains(SrcReg))
108 else if (Mips::LO32DSPRegClass.contains(SrcReg))
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MipsFastISel.cpp 183 bool emitStore(MVT VT, unsigned SrcReg, Address Addr,
185 bool emitStore(MVT VT, unsigned SrcReg, Address &Addr,
187 unsigned emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
188 bool emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg,
191 bool emitIntZExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
193 bool emitIntSExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
194 bool emitIntSExt32r1(MVT SrcVT, unsigned SrcReg, MVT DestVT,
196 bool emitIntSExt32r2(MVT SrcVT, unsigned SrcReg, MVT DestVT,
219 MachineInstrBuilder emitInstStore(unsigned Opc, unsigned SrcReg,
221 return emitInst(Opc).addReg(SrcReg).addReg(MemReg).addImm(MemOffset)
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  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/MCTargetDesc/
HexagonMCDuplexInfo.cpp 190 unsigned DstReg, PredReg, SrcReg, Src1Reg, Src2Reg;
202 SrcReg = MCI.getOperand(1).getReg();
206 if (HexagonMCInstrInfo::isIntReg(SrcReg) &&
207 Hexagon::R29 == SrcReg && inRange<5, 2>(MCI, 2)) {
211 if (HexagonMCInstrInfo::isIntRegForSubInst(SrcReg) &&
220 SrcReg = MCI.getOperand(1).getReg();
222 HexagonMCInstrInfo::isIntRegForSubInst(SrcReg) &&
241 SrcReg = MCI.getOperand(1).getReg();
243 HexagonMCInstrInfo::isIntRegForSubInst(SrcReg) &&
251 SrcReg = MCI.getOperand(1).getReg()
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  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86LowerTileCopy.cpp 85 Register SrcReg = SrcMO.getReg();
87 if (!X86::TILERegClass.contains(DstReg, SrcReg))
115 .addReg(SrcReg, getKillRegState(SrcMO.isKill()));
  /src/external/apache2/llvm/dist/llvm/lib/Target/AVR/
AVRExpandPseudoInsts.cpp 146 Register SrcReg = MI.getOperand(2).getReg();
151 TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg);
179 Register SrcReg = MI.getOperand(2).getReg();
184 TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg);
461 Register SrcReg = MI.getOperand(1).getReg();
467 TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg);
494 Register SrcReg = MI.getOperand(1).getReg();
500 TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg);
623 Register SrcReg = MI.getOperand(1).getReg();
630 if (DstReg == SrcReg)
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