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    Searched refs:SrcReg0Sub0 (Results 1 - 2 of 2) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
SIInstrInfo.cpp 6342 MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
6350 MachineInstr &LoHalf = *BuildMI(MBB, MII, DL, InstDesc, DestSub0).add(SrcReg0Sub0);
6407 MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
6422 .add(SrcReg0Sub0)
6477 MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
6492 .add(SrcReg0Sub0)
SIISelLowering.cpp 3977 MachineOperand SrcReg0Sub0 = TII->buildExtractSubRegOrImm(
3990 .add(SrcReg0Sub0)

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