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    Searched refs:SrcReg0Sub1 (Results 1 - 2 of 2) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
SIInstrInfo.cpp 6352 MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
6356 MachineInstr &HiHalf = *BuildMI(MBB, MII, DL, InstDesc, DestSub1).add(SrcReg0Sub1);
6413 MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
6430 .add(SrcReg0Sub1)
6481 MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
6497 .add(SrcReg0Sub1)
SIISelLowering.cpp 3982 MachineOperand SrcReg0Sub1 = TII->buildExtractSubRegOrImm(
3998 .add(SrcReg0Sub1)

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