| /src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/ |
| LanaiInstrInfo.h | 96 // SrcReg2 if having two register operands, and the value it compares against
99 Register &SrcReg2, int &CmpMask,
106 Register SrcReg2, int CmpMask, int CmpValue,
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| LanaiInstrInfo.cpp | 178 Register &SrcReg2, int &CmpMask,
186 SrcReg2 = Register();
192 SrcReg2 = MI.getOperand(1).getReg();
206 unsigned SrcReg2, int ImmValue,
211 OI->getOperand(2).getReg() == SrcReg2) ||
212 (OI->getOperand(1).getReg() == SrcReg2 &&
284 MachineInstr &CmpInstr, Register SrcReg, Register SrcReg2, int /*CmpMask*/,
304 if (SrcReg2 != 0)
330 if (isRedundantFlagInstr(&CmpInstr, SrcReg, SrcReg2, CmpValue, &*I)) {
382 if (SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 &
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/ |
| SystemZElimCompare.cpp | 627 // SrcReg2 is the register if the source operand is a register,
631 Register SrcReg2 =
636 (SrcReg2 && MBBI->modifiesRegister(SrcReg2, TRI)))
690 // Clear any intervening kills of SrcReg and SrcReg2.
694 if (SrcReg2)
695 MBBI->clearRegisterKills(SrcReg2, TRI);
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| SystemZInstrInfo.h | 237 Register &SrcReg2, int &Mask, int &Value) const override;
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| SystemZInstrInfo.cpp | 517 Register &SrcReg2, int &Mask,
524 SrcReg2 = 0;
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| /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| PPCFastISel.cpp | 854 unsigned SrcReg2 = 0;
856 SrcReg2 = getRegForValue(SrcValue2);
857 if (SrcReg2 == 0)
865 auto RC2 = SrcReg2 != 0 ? MRI.getRegClass(SrcReg2) : nullptr;
888 SrcReg2 = copyRegToRegClass(&PPC::F4RCRegClass, SrcReg2);
938 if (!PPCEmitIntExt(SrcVT, SrcReg2, MVT::i32, ExtReg, IsZExt))
940 SrcReg2 = ExtReg;
946 .addReg(SrcReg1).addReg(SrcReg2);
[all...] |
| PPCInstrInfo.h | 522 Register &SrcReg2, int &Mask, int &Value) const override;
525 Register SrcReg2, int Mask, int Value,
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| PPCInstrInfo.cpp | 2328 Register &SrcReg2, int &Mask,
2339 SrcReg2 = 0;
2350 SrcReg2 = MI.getOperand(2).getReg();
2358 Register SrcReg2, int Mask, int Value,
2464 if (SrcReg2 != 0)
2539 Instr.getOperand(2).getReg() == SrcReg2) ||
2540 (Instr.getOperand(1).getReg() == SrcReg2 &&
2594 ShouldSwap = SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 &&
5313 Register SrcReg2 = MI.getOperand(2).getReg()
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| AArch64InstrInfo.h | 227 /// in SrcReg and SrcReg2, and the value it compares against in CmpValue.
230 Register &SrcReg2, int &CmpMask,
235 Register SrcReg2, int CmpMask, int CmpValue,
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| AArch64SIMDInstrOpt.cpp | 441 Register SrcReg2 = MI.getOperand(3).getReg();
447 if (!reuseDUP(MI, DupMCID->getOpcode(), SrcReg2, LaneNumber, &DupDest)) {
450 .addReg(SrcReg2, Src2IsKill)
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| AArch64InstrInfo.cpp | 1112 /// in SrcReg and SrcReg2, and the value it compares against in CmpValue.
1115 Register &SrcReg2, int &CmpMask,
1128 SrcReg2 = MI.getOperand(1).getReg();
1147 SrcReg2 = MI.getOperand(2).getReg();
1156 SrcReg2 = 0;
1166 SrcReg2 = 0;
1436 MachineInstr &CmpInstr, Register SrcReg, Register SrcReg2, int CmpMask,
1463 return optimizePTestInstr(&CmpInstr, SrcReg, SrcReg2, MRI);
1469 if (SrcReg2 != 0)
5020 unsigned SrcReg2;
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| X86InstrInfo.h | 505 /// in SrcReg and SrcReg2 if having two register operands, and the value it
509 Register &SrcReg2, int &CmpMask,
516 Register SrcReg2, int CmpMask, int CmpValue,
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| X86InstrInfo.cpp | 1537 Register SrcReg2;
1540 SrcReg2, isKill2, ImplicitOp2, LV))
1549 NewMI = addRegReg(MIB, SrcReg, isKill, SrcReg2, isKill2);
1551 LV->replaceKillInstruction(SrcReg2, MI, *NewMI);
3855 Register &SrcReg2, int &CmpMask,
3867 SrcReg2 = 0;
3881 SrcReg2 = 0;
3890 SrcReg2 = MI.getOperand(2).getReg();
3902 SrcReg2 = 0;
3915 SrcReg2 = MI.getOperand(1).getReg()
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| ARMFastISel.cpp | 1412 unsigned SrcReg2 = 0;
1414 SrcReg2 = getRegForValue(Src2Value);
1415 if (SrcReg2 == 0) return false;
1423 SrcReg2 = ARMEmitIntExt(SrcVT, SrcReg2, MVT::i32, isZExt);
1424 if (SrcReg2 == 0) return false;
1431 SrcReg2 = constrainOperandRegClass(II, SrcReg2, 1);
1433 .addReg(SrcReg1).addReg(SrcReg2));
1760 unsigned SrcReg2 = getRegForValue(I->getOperand(1))
[all...] |
| ARMBaseInstrInfo.cpp | 2769 /// in SrcReg and SrcReg2 if having two register operands, and the value it
2773 Register &SrcReg2, int &CmpMask,
2781 SrcReg2 = 0;
2789 SrcReg2 = MI.getOperand(1).getReg();
2796 SrcReg2 = 0;
2844 Register SrcReg, Register SrcReg2,
2850 OI->getOperand(2).getReg() == SrcReg2) ||
2851 (OI->getOperand(1).getReg() == SrcReg2 &&
2859 OI->getOperand(3).getReg() == SrcReg2) ||
2860 (OI->getOperand(2).getReg() == SrcReg2 &
[all...] |
| ARMBaseInstrInfo.h | 288 /// in SrcReg and SrcReg2 if having two register operands, and the value it
292 Register &SrcReg2, int &CmpMask,
300 Register SrcReg2, int CmpMask, int CmpValue,
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| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| PeepholeOptimizer.cpp | 613 Register SrcReg, SrcReg2;
615 if (!TII->analyzeCompare(MI, SrcReg, SrcReg2, CmpMask, CmpValue) ||
616 SrcReg.isPhysical() || SrcReg2.isPhysical())
621 if (TII->optimizeCompareInstr(MI, SrcReg, SrcReg2, CmpMask, CmpValue, MRI)) {
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| /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| HexagonInstrInfo.h | 269 /// in SrcReg and SrcReg2 if having two register operands, and the value it
273 Register &SrcReg2, int &Mask, int &Value) const override;
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| HexagonInstrInfo.cpp | 1790 /// \p SrcReg and \p SrcReg2 if having two register operands, and the value it
1794 Register &SrcReg2, int &Mask,
1855 SrcReg2 = MI.getOperand(2).getReg();
1870 SrcReg2 = 0;
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| /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| TargetInstrInfo.h | 1523 /// in SrcReg and SrcReg2 if having two register operands, and the value it
1527 Register &SrcReg2, int &Mask, int &Value) const {
1535 Register SrcReg2, int Mask, int Value,
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