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    Searched refs:Srl (Results 1 - 6 of 6) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
AMDGPUISelDAGToDAG.cpp 332 SDValue Srl = In.getOperand(0);
333 if (Srl.getOpcode() == ISD::SRL) {
334 if (ConstantSDNode *ShiftAmt = dyn_cast<ConstantSDNode>(Srl.getOperand(1))) {
336 Out = stripBitcast(Srl.getOperand(0));
860 case ISD::SRL:
2135 // "(a << b) srl c)" ---> "BFE_U32 a, (c-b), (32-c)
2162 if (N->getOperand(0).getOpcode() == ISD::SRL) {
2163 // "(a srl b) & mask" ---> "BFE_U32 a, b, popcount(mask)"
2165 const SDValue &Srl = N->getOperand(0)
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SIISelLowering.cpp 669 setOperationAction(ISD::SRL, MVT::v2i16, Legal);
698 setOperationAction(ISD::SRL, MVT::v4i16, Custom);
1694 SDValue Extract = DAG.getNode(ISD::SRL, SL, MVT::i32, Load, ShiftAmt);
4535 case ISD::SRL:
5148 DAG.getNode(UseArithShift ? ISD::SRA : ISD::SRL,
5499 SDValue Elt = DAG.getNode(ISD::SRL, SL, IntVT, BC, ScaledIdx);
8055 SDValue Elt = DAG.getNode(ISD::SRL, DL, MVT::i32, NewLD,
9004 case ISD::SRL:
9033 // and (srl x, c), mask => shl (bfe x, nb + c, mask >> nb), nb
9039 if (getSubtarget()->hasSDWA() && LHS->getOpcode() == ISD::SRL &
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  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMISelDAGToDAG.cpp 410 // Look for (add X1, (and (srl X2, c1), c2)) where c2 is constant with
414 // (add X1, (shl (and (srl X2, c1), (c2>>tz)), tz)) where tz is the number
416 // operand of 'add' and the 'and' and 'srl' would become a bits extraction
446 // Look for (and (srl X, c1), c2).
447 SDValue Srl = N1.getOperand(0);
449 if (!isOpcWithIntImmediate(Srl.getNode(), ISD::SRL, Srl_imm) ||
468 Srl = CurDAG->getNode(ISD::SRL, SDLoc(Srl), MVT::i32
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  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
DAGCombiner.cpp 1373 else if (Opc == ISD::SRL)
1651 case ISD::SRL: return visitSRL(N);
1778 case ISD::SRL:
2214 // logical shift right: add (srl), C or sub C, (srl).
2219 ShiftOp.getOpcode() != ISD::SRL)
2235 // add (srl (not X), 31), C --> add (sra X, 31), (C + 1)
2236 // sub C, (srl (not X), 31) --> add (srl X, 31), (C - 1)
2238 auto ShOpcode = IsAdd ? ISD::SRA : ISD::SRL;
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  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86ISelDAGToDAG.cpp 694 case ISD::SRL:
1019 case ISD::SRL: {
1030 case ISD::SRL: NewOpc = X86ISD::VSRLV; break;
1840 if (Shift.getOpcode() != ISD::SRL ||
1854 SDValue Srl = DAG.getNode(ISD::SRL, DL, VT, X, Eight);
1855 SDValue And = DAG.getNode(ISD::AND, DL, VT, Srl, NewMask);
1865 insertDAGNode(DAG, N, Srl);
1947 // scale. Patterns such as (shl (srl x, c1), c2) are canonicalized into (and
1948 // (srl x, SHIFT), MASK) by DAGCombines that don't know the shl can be done i
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  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/
LegalizerHelper.cpp 5425 // fshl X, Y, Z -> fshr (srl X, 1), (fshr X, Y, 1), ~Z
5812 auto Srl = MIRBuilder.buildLShr(DstTy, R, ExponentSub);
5818 R = MIRBuilder.buildSelect(DstTy, CmpGt, Shl, Srl);

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