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    Searched refs:Strategy (Results 1 - 11 of 11) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/include/llvm/Analysis/
DomTreeUpdater.h 32 explicit DomTreeUpdater(UpdateStrategy Strategy_) : Strategy(Strategy_) {}
34 : DT(&DT_), Strategy(Strategy_) {}
36 : DT(DT_), Strategy(Strategy_) {}
38 : PDT(&PDT_), Strategy(Strategy_) {}
40 : PDT(PDT_), Strategy(Strategy_) {}
43 : DT(&DT_), PDT(&PDT_), Strategy(Strategy_) {}
46 : DT(DT_), PDT(PDT_), Strategy(Strategy_) {}
50 /// Returns true if the current strategy is Lazy.
51 bool isLazy() const { return Strategy == UpdateStrategy::Lazy; };
53 /// Returns true if the current strategy is Eager
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Analysis/
DomTreeUpdater.cpp 59 if (Strategy != UpdateStrategy::Lazy || !DT)
80 if (Strategy != UpdateStrategy::Lazy || !PDT)
122 if (Strategy == UpdateStrategy::Eager) {
167 if (Strategy == UpdateStrategy::Eager || DeletedBBs.empty())
179 if (Strategy == UpdateStrategy::Lazy) {
192 if (Strategy == UpdateStrategy::Lazy) {
234 if (Strategy == UpdateStrategy::Lazy) {
294 if (Strategy == UpdateStrategy::Lazy)
331 if (Strategy == UpdateStrategy::Eager) {
352 if (Strategy == UpdateStrategy::Eager)
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
ExpandVectorPredication.cpp 331 TargetTransformInfo::VPLegalization Strategy;
333 : PI(PI), Strategy(InitStrat) {}
335 bool isDone() const { return Strategy.shouldDoNothing(); }
379 // strategy.
397 switch (Job.Strategy.EVLParamStrategy) {
408 Job.Strategy.EVLParamStrategy = VPLegalization::Legal;
411 switch (Job.Strategy.OpStrategy) {
415 llvm_unreachable("Invalid strategy for operators.");
421 Job.Strategy.OpStrategy = VPLegalization::Legal;
MachineTraceMetrics.cpp 94 // those instructions don't depend on any given trace strategy.
288 // A trace selection strategy is implemented as a sub-class of Ensemble. The
382 // Get an Ensemble sub-class for the requested trace strategy.
384 MachineTraceMetrics::getEnsemble(MachineTraceMetrics::Strategy strategy) {
385 assert(strategy < TS_NumStrategies && "Invalid trace strategy enum");
386 Ensemble *&E = Ensembles[strategy];
391 switch (strategy) {
393 default: llvm_unreachable("Invalid trace strategy enum")
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/FuzzMutate/
IRMutator.cpp 62 for (const auto &Strategy : Strategies)
63 RS.sample(Strategy.get(),
64 Strategy->getWeight(CurSize, MaxSize, RS.totalWeight()));
65 auto Strategy = RS.getSelection();
67 Strategy->mutate(M, IB);
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
GCNIterativeScheduler.h 77 const StrategyKind Strategy;
GCNIterativeScheduler.cpp 226 , Strategy(S)
310 switch (Strategy) {
426 // Legacy MaxOccupancy Strategy
524 // Minimal Register Strategy
  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
MachineTraceMetrics.h 319 /// strategy, for example 'minimum resource height'. There is one trace for
377 enum Strategy {
384 /// Get the trace ensemble representing the given trace selection strategy.
387 Ensemble *getEnsemble(Strategy);
410 // One ensemble per strategy.
  /src/external/apache2/llvm/dist/llvm/utils/TableGen/
X86FoldTablesEmitter.cpp 36 UnfoldStrategy Strategy;
39 UnfoldStrategy Strategy = NO_STRATEGY)
40 : RegInstStr(RegInstStr), MemInstStr(MemInstStr), Strategy(Strategy) {}
161 // S sets the strategy of adding the TB_NO_REVERSE flag.
654 &(Target.getInstruction(MemInstIter)), Entry.Strategy);
  /src/external/apache2/llvm/dist/llvm/include/llvm/MCA/HardwareUnits/
Scheduler.h 39 /// Default instruction selection strategy used by class Scheduler.
73 // Instruction selection strategy for this Scheduler.
74 std::unique_ptr<SchedulerStrategy> Strategy;
131 /// Verify the given selection strategy and set the Strategy member
132 /// accordingly. If no strategy is provided, the DefaultSchedulerStrategy is
  /src/external/apache2/llvm/dist/llvm/lib/MCA/HardwareUnits/
Scheduler.cpp 23 // Ensure we have a valid (non-null) strategy object.
24 Strategy = S ? std::move(S) : std::make_unique<DefaultSchedulerStrategy>();
197 Strategy->compare(IR, ReadySet[QueueIndex])) {

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